Self-concatenated code design and its application in power-efficient cooperative communications

In this tutorial, we have focused on the design of binary self-concatenated coding schemes with the help of EXtrinsic Information Transfer (EXIT) charts and Union bound analysis. The design methodology of future iteratively decoded self-concatenated aided cooperative communication schemes is presented. In doing so, we will identify the most important milestones in the area of channel coding, concatenated coding schemes and cooperative communication systems till date and suggest future research directions

VLSI implementation of a multi-mode turbo/LDPC decoder architecture

Flexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, reconfigurable architectures for the physical layer are an attractive solution not only to switch among different coding modes but also to achieve interoperability. This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding. The novel contributions of this paper are: i) tackling the reconfiguration issue introducing a formal and systematic treatment that, to the best of our knowledge, was not previously addressed; ii) proposing a reconfigurable NoCbased turbo/LDPC decoder architecture and showing that wide flexibility can be achieved with a small complexity overhead. Obtained results show that dynamic switching between most of considered communication standards is possible without pausing the decoding activity. Moreover, post-layout results show that tailoring the proposed architecture to the WiMAX standard leads to an area occupation of 2.75 mm2 and a power consumption of 101.5 mW in the worst case

EXIT charts for system design and analysis

Near-capacity performance may be achieved with the aid of iterative decoding, where extrinsic soft information is exchanged between the constituent decoders in order to improve the attainable system performance. Extrinsic information Transfer (EXIT) charts constitute a powerful semi-analytical tool used for analysing and designing iteratively decoded systems. In this tutorial, we commence by providing a rudimentary overview of the iterative decoding principle and the concept of soft information exchange. We then elaborate on the concept of EXIT charts using three iteratively decoded prototype systems as design examples. We conclude by illustrating further applications of EXIT charts, including near-capacity designs, the concept of irregular codes and the design of modulation schemes

Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures

This work proposes a general framework for the design and simulation of network on chip based turbo decoder architectures. Several parameters in the design space are investigated, namely the network topology, the parallelism degree, the rate at which messages are sent by processing nodes over the network and the routing strategy. The main results of this analysis are: i) the most suited topologies to achieve high throughput with a limited complexity overhead are generalized de-Bruijn and generalized Kautz topologies; ii) depending on the throughput requirements different parallelism degrees, message injection rates and routing algorithms can be used to minimize the network area overhead.Comment: submitted to IEEE Trans. on Circuits and Systems I (submission date 27 may 2009

Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation

HomePlug AV is the most successful standard for in home power line communications. To combat non-ideality of the power line channel it includes a double binary turbo forward error correcting scheme. Unfortunately, it is known that the memory required by double binary turbo decoders for iteration-exchanged information is roughly three times the memory required for binary turbo codes. Moreover, high throughput implementations based on border state metric inheritance, require additional memories to store border state metrics from an iteration to the next one. This work faces these two aspects by analyzing compression techniques to reduce the amount of memory required to store both iteration-exchanged information and border future metrics. Experimental simulations show that non-uniform quantization and least significant bits dropping allow for a significant memory reduction (up to 30%) with a bit error rate performance loss of about 0.1 dB and a negligible logic gates overhead

Iterative Decoding and Turbo Equalization: The Z-Crease Phenomenon

Iterative probabilistic inference, popularly dubbed the soft-iterative paradigm, has found great use in a wide range of communication applications, including turbo decoding and turbo equalization. The classic approach of analyzing the iterative approach inevitably use the statistical and information-theoretical tools that bear ensemble-average flavors. This paper consider the per-block error rate performance, and analyzes it using nonlinear dynamical theory. By modeling the iterative processor as a nonlinear dynamical system, we report a universal "Z-crease phenomenon:" the zig-zag or up-and-down fluctuation -- rather than the monotonic decrease -- of the per-block errors, as the number of iteration increases. Using the turbo decoder as an example, we also report several interesting motion phenomenons which were not previously reported, and which appear to correspond well with the notion of "pseudo codewords" and "stopping/trapping sets." We further propose a heuristic stopping criterion to control Z-crease and identify the best iteration. Our stopping criterion is most useful for controlling the worst-case per-block errors, and helps to significantly reduce the average-iteration numbers.Comment: 6 page