23,933 research outputs found
FPGA Implementation of Hand-written Number Recognition Based on CNN
Convolutional Neural Networks (CNNs) are the state-of-the-art in computer vision for different purposes such as image and video classification, recommender systems and natural language processing. The connectivity pattern between CNNs neurons is inspired by the structure of the animal visual cortex. In order to allow the processing, they are realized with multiple parallel 2-dimensional FIR filters that convolve the input signal with the learned feature maps. For this reason, a CNN implementation requires highly parallel computations that cannot be achieved using traditional general-purpose processors, which is why they benefit from a very significant speed-up when mapped and run on Field Programmable Gate Arrays (FPGAs). This is because FPGAs offer the capability to design full customizable hardware architectures, providing high flexibility and the availability of hundreds to thousands of on-chip Digital Signal Processing (DSP) blocks. This paper presents an FPGA implementation of a hand-written number recognition system based on CNN. The system has been characterized in terms of classification accuracy, area, speed, and power consumption. The neural network was implemented on a Xilinx XC7A100T FPGA, and it uses 29.69% of Slice LUTs, 4.42% of slice registers and 52.50% block RAMs. We designed the system using a 9-bit representation that allows for avoiding the use of DSP. For this reason, multipliers are implemented using LUTs. The proposed architecture can be easily scaled on different FPGA devices thank its regularity. CNN can reach a classification accuracy of 90%
Spaceborne memory organization Interim report
Associative memory applications in unmanned space vehicle
Spaceborne memory organization, phase 1 Final report
Application of associative memories to data processing for future space vehicle
Two Hardware Implementations of the Exhaustive Synthetic AER Generation Method
Address-Event-Representation (AER) is a communications protocol
for transferring images between chips, originally developed for bio-inspired
image processing systems. In [6], [5] various software methods for synthetic
AER generation were presented. But in neuro-inspired research field, hardware
methods are needed to generate AER from laptop computers. In this paper two
real time implementations of the exhaustive method, proposed in [6], [5], are
presented. These implementations can transmit, through AER bus, images
stored in a computer using USB-AER board developed by our RTCAR group
for the CAVIAR EU project.Commission of the European Communities IST-2001-34124 (CAVIAR)Comisión Interministerial de Ciencia y Tecnología TIC-2003-08164-C03-0
Emulating Digital Logic using Transputer Networks (Very High Parallelism = Simplicity = Performance)
Modern VLSI technology has changed the economic rules by which the balance between processing
power, memory and communications is decided in computing systems. This will have a profound
impact on the design rules for the controlling software. In particular, the criteria for judging efficiency
of the algorithms will be somewhat different. This paper explores some of these implications through
the development of highly parallel and highly distributable algorithms based on occam and transputer
networks. The major results reported are a new simplicity for software designs, a corresponding ability
to reason (formally and informally) about their properties, the reusability of their components and some
real performance figures which demonstrate their practicality. Some guidelines to assist in these designs
are also given. As a vehicle for discussion, an interactive simulator is developed for checking the
functional and timing characteristics of digital logic circuits of arbitrary complexity
An FPGA Architecture for Extracting Real-Time Zernike Coefficients from Measured Phase Gradients
Zernike modes are commonly used in adaptive optics systems to represent optical wavefronts. However, real-time calculation of Zernike modes is time consuming due to two factors: the large factorial components in the radial polynomials used to define them and the large inverse matrix calculation needed for the linear fit. This paper presents an efficient parallel method for calculating Zernike coefficients from phase gradients produced by a Shack-Hartman sensor and its real-time implementation using an FPGA by pre-calculation and storage of subsections of the large inverse matrix. The architecture exploits symmetries within the Zernike modes to achieve a significant reduction in memory requirements and a speed-up of 2.9 when compared to published results utilising a 2D-FFT method for a grid size of 8×8. Analysis of processor element internal word length requirements show that 24-bit precision in precalculated values of the Zernike mode partial derivatives ensures less than 0.5% error per Zernike coefficient and an overall error of <1%. The design has been synthesized on a Xilinx Spartan-6 XC6SLX45 FPGA. The resource utilisation on this device is <3% of slice registers, <15% of slice LUTs, and approximately 48% of available DSP blocks independent of the Shack-Hartmann grid size. Block RAM usage is <16% for Shack-Hartmann grid sizes up to 32×32
The S2 VLBI Correlator: A Correlator for Space VLBI and Geodetic Signal Processing
We describe the design of a correlator system for ground and space-based
VLBI. The correlator contains unique signal processing functions: flexible LO
frequency switching for bandwidth synthesis; 1 ms dump intervals, multi-rate
digital signal-processing techniques to allow correlation of signals at
different sample rates; and a digital filter for very high resolution
cross-power spectra. It also includes autocorrelation, tone extraction, pulsar
gating, signal-statistics accumulation.Comment: 44 pages, 13 figure
A reconfigurable real-time morphological system for augmented vision
There is a significant number of visually impaired individuals who suffer sensitivity loss to high spatial frequencies, for whom current optical devices are limited in degree of visual aid and practical application. Digital image and video processing offers a variety of effective visual enhancement methods that can be utilised to obtain a practical augmented vision head-mounted display device. The high spatial frequencies of an image can be extracted by edge detection techniques and overlaid on top of the original image to improve visual perception among the visually impaired. Augmented visual aid devices require highly user-customisable algorithm designs for subjective configuration per task, where current digital image processing visual aids offer very little user-configurable options. This paper presents a highly user-reconfigurable morphological edge enhancement system on field-programmable gate array, where the morphological, internal and external edge gradients can be selected from the presented architecture with specified edge thickness and magnitude. In addition, the morphology architecture supports reconfigurable shape structuring elements and configurable morphological operations. The proposed morphology-based visual enhancement system introduces a high degree of user flexibility in addition to meeting real-time constraints capable of obtaining 93 fps for high-definition image resolution
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