Analog, hybrid, and digital simulation

Analog, hybrid, and digital computerized simulation technique

A study of high density bit transition requirements versus the effects on BCH error correcting codes

The use of PN sequence generators to create a minimum number of transitions in an NRZ bit stream is described. The CSG encoder/decoder design was constructed and demonstrated

A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS

An eye-opening monitor (EOM) architecture that can capture a two-dimensional (2-D) map of the eye diagram of a high-speed data signal has been developed. Two single-quadrant phase rotators and one digital-to-analog converter (DAC) are used to generate rectangular masks with variable sizes and aspect ratios. Each mask is overlapped with the received eye diagram and the number of signal transitions inside the mask is recorded as error. The combination of rectangular masks with the same error creates error contours that overall provide a 2-D map of the eye. The authors have implemented a prototype circuit in 0.13-μm standard CMOS technology that operates up to 12.5 Gb/s at 1.2-V supply. The EOM maps the input eye to a 2-D error diagram with up to 68-dB mask error dynamic range. The left and right halves of the eyes are monitored separately to capture horizontally asymmetric eyes. The chip consumes 330 mW and operates reliably with supply voltages as low as 1 V at 10 Gb/s. The authors also present a detailed analysis that verifies if the measurements are in good agreement with the expected results

A system for the simulation and evaluation of satellite communication networks

With the emergence of a new era in satellite communications brought about by NASA's thrust into the Ka band with multibeam and onboard processing technologies, new and innovative techniques for evaluating these concepts and systems are required. To this end, NASA, in conjunction with its extensive program for advanced communications technology development, has undertaken to develop a concept for the simulation and evaluation of a complete communications network. Incorporated in this network will be proof of concept models of the latest technologies proposed for future satellite communications systems. These include low noise receivers, matrix switches, baseband processors, and solid state and tube type high power amplifiers. To accomplish this, numerous supporting technologies must be added to those aforementioned proof of concept models. These include controllers for synchronization, order wire, and resource allocation, gain compensation, signal leveling, power augmentation, and rain fade and range delay simulation. Taken together, these will be assembled to comprise a system capable of addressing numerous design and performance questions. The simulation and evaluation system as planned will be modular in design and implementation, capable of modification and updating to track and evaluate a continuum emerging concepts and technologies

A Novel TRNG Based on Traditional ADC Nonlinear Effect and Chaotic Map for IoT Security and Anticollision

In the rapidly developing Internet of Things (IoT) applications, how to achieve rapid identification of massive devices and secure the communication of wireless data based on low cost and low power consumption is the key problem to be solved urgently. This paper proposes a novel true random number generator (TRNG) based on ADC nonlinear effect and chaotic map, which can be implemented by traditional processors with built-in ADCs, such as MCU, DSP, ARM, and FPGA. The processor controls the ADC to sample the changing input signal to obtain the digital signal DADC and then extracts some bits of DADC to generate the true random number (TRN). At the same time, after a delay based on DADC, the next time ADC sampling is carried out, and the cycle continues until the processor stops generating the TRN. Due to the nonlinear effect of ADC, the DADC obtained from each sampling is stochastic, and the changing input signal will sharply change the delay time, thus changing the sampling interval (called random interval sampling). As the input signal changes, DADC with strong randomness is obtained. The whole operation of the TRNG resembles a chaotic map, and this method also eliminates the pseudorandom property of chaotic map by combining the variable input signal (including noise) with the nonlinear effect of ADC. The simulation and actual test data are verified by NIST, and the verification results show that the random numbers generated by the proposed method have strong randomness and can be used to implement TRNG. The proposed TRNG has the advantages of low cost, low power consumption, and strong compatibility, and the rate of generating true random number is more than 1.6 Mbps (determined by ADC sampling rate and processor frequency), which is very suitable for IoT sensor devices for security encryption algorithms and anticollision

Communication Robustness Analysis and improvements in Leclanch'e BMS systems

This master thesis have been done in the circumstance of an internship contract in a Swiss company called Leclanch'e SA. This company is develops, designs and manufactures complete battery storage solutions, covering the entire technology chain. From cells to pack solutions for Hybrid Electric Vehicles (HEVs) and Battery Electric Vehicles (BEVs), as well as the Battery Management System which is the scope of this thesis. Customers of the company have reported errors on the communication interface of the Battery Management System of the company, known as G2 Leclanché BMS. The purpose of the study done in this thesis is to find root causes of problems in the communication interface and its constraints. To this end, faulty BMS samples returned by clients have been analysed and some special testing setups have been prepared in order to study communication constraints as baud rate, cable length, maximum number of nodes, etc. Conclusions extracted from this robustness analysis of communication on G2 Leclanch'e BMS will be used for the next generation of BMS which is being developed by the company

Application of bit-slice microprocessors to digital correlation in spread spectrum communication systems

This thesis describes the application of commercially available microprocessors and other VLSI devices to high-speed real-time digital correlation in spread spectrum and related communication applications. Spread spectrum communications are a wide-band secure communication system that generate a very broad spectral bandwidth signal that is therefore hard to detect in noise. They are capable of rejecting intentional or unintentional jamming, and are insensitive to the multipath and fading that affects conventional high frequency systems. The bandwidth of spread spectrum systems must be large to obtain a significant performance improvement. This means that the sequence rate must be fast and therefore very fast microprocessors will be required when they are used to perform spread spectrum correlation. Since multiplication cannot be performed efficiently by microprocessors considerable work, since 1974, has been published in the literature which is devoted to minimising the requirement of multiplications in digital correlation and other signal processing algorithms. These fast techniques are investigated and implemented using general-purpose microprocessors. The restricted-bandwidth problem in microprocessor-based digital correlator has been discussed. A new implementation is suggested which uses bit-slice devices to maintain the flexibility of microprocessor-based digital correlation without sacrificing speed. This microprocessor-based system has been found to be efficient in implementing the correlation process at the baseband in the digital domain as well as the post-correlation signal processing- demodulation, detection and tracking, especiaJIy for low rate signals. A charge coupled-device is used to obtain spectral density function. An all-digital technique which is programmable for any binary waveform and can be used for achieving initial acquisition and maintaining synchronisation in spread spectrum communications is described. Many of the practical implementation problems are discussed. The receiver performance, which is measured in terms of the acquisition time and the bit-error rate, is also presented and results are obtained which are close to those predicted in the system simulations