4 research outputs found
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
Comunicación presentada al "Iberchip XVIII Workshop " celebrado en Playa del Carmen (México) del 29 de Febrero al 2 de Marzo del 2012.-- Presentado posteriormente al "19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)" celebrado en Sevilla (España) del 9 al 12 de Diciembre del 2012.The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an IV characteristic exhibiting Negative Differential Resistance (NDR) built from MOS transistors plus an inductor and a resistor. Frequency division is obtained from the period adding sequences which appear in its bifurcation diagram. The analyzed circuit is an “all MOS” version of one previously reported which use Resonant Tunneling Diodes (RTDs) The results show that the dividing ratio can be selected by modulating the input signal frequency, in a similar way to the RTD-based circuit.Gobierno de España TEC2007-67245/MICJunta de Andalucía. Consejería de Innovación, Ciencia y Empresas P07-TIC-0296
Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS
Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop.
Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes.
With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor
Bibliography of Lewis Research Center technical publications announced in 1993
This compilation of abstracts describes and indexes the technical reporting that resulted from the scientific and engineering work performed and managed by the Lewis Research Center in 1993. All the publications were announced in the 1993 issues of STAR (Scientific and Technical Aerospace Reports) and/or IAA (International Aerospace Abstracts). Included are research reports, journal articles, conference presentations, patents and patent applications, and theses
Proceedings of the First International Conference on Heat Transfer, Fluid Mechanics and Thermodynamics
1st International Conference on Heat Transfer, Fluid Mechanics and Thermodynamics, Kruger Park, 8-10 April 2002.This lecture is a principle-based review of a growing body
of fundamental work stimulated by multiple opportunities to
optimize geometric form (shape, structure, configuration,
rhythm, topology, architecture, geography) in systems for heat
and fluid flow. Currents flow against resistances, and by
generating entropy (irreversibility) they force the system global
performance to levels lower than the theoretical limit. The
system design is destined to remain imperfect because of
constraints (finite sizes, costs, times). Improvements can be
achieved by properly balancing the resistances, i.e., by spreading
the imperfections through the system. Optimal spreading means
to endow the system with geometric form. The system
construction springs out of the constrained maximization of
global performance. This 'constructal' design principle is
reviewed by highlighting applications from heat transfer
engineering. Several examples illustrate the optimized internal
structure of convection cooled packages of electronics. The
origin of optimal geometric features lies in the global effort to
use every volume element to the maximum, i.e., to pack the
element not only with the most heat generating components, but
also with the most flow, in such a way that every fluid packet is
effectively engaged in cooling. In flows that connect a point to
a volume or an area, the resulting structure is a tree with high conductivity
branches and low-conductivity interstices.tm201