45-nm Radiation Hardened Cache Design

abstract: Circuits on smaller technology nodes become more vulnerable to radiation-induced upset. Since this is a major problem for electronic circuits used in space applications, designers have a variety of solutions in hand. Radiation hardening by design (RHBD) is an approach, where electronic components are designed to work properly in certain radiation environments without the use of special fabrication processes. This work focuses on the cache design for a high performance microprocessor. The design tries to mitigate radiation effects like SEE, on a commercial foundry 45 nm SOI process. The design has been ported from a previously done cache design at the 90 nm process node. The cache design is a 16 KB, 4 way set associative, write-through design that uses a no-write allocate policy. The cache has been tested to write and read at above 2 GHz at VDD = 0.9 V. Interleaved layout, parity protection, dual redundancy, and checking circuits are used in the design to achieve radiation hardness. High speed is accomplished through the use of dynamic circuits and short wiring routes wherever possible. Gated clocks and optimized wire connections are used to reduce power. Structured methodology is used to build up the entire cache.Dissertation/ThesisM.S. Electrical Engineering 201

Efficient modular arithmetic units for low power cryptographic applications

The demand for high security in energy constrained devices such as mobiles and PDAs is growing rapidly. This leads to the need for efficient design of cryptographic algorithms which offer data integrity, authentication, non-repudiation and confidentiality of the encrypted data and communication channels. The public key cryptography is an ideal choice for data integrity, authentication and non-repudiation whereas the private key cryptography ensures the confidentiality of the data transmitted. The latter has an extremely high encryption speed but it has certain limitations which make it unsuitable for use in certain applications. Numerous public key cryptographic algorithms are available in the literature which comprise modular arithmetic modules such as modular addition, multiplication, inversion and exponentiation. Recently, numerous cryptographic algorithms have been proposed based on modular arithmetic which are scalable, do word based operations and efficient in various aspects. The modular arithmetic modules play a crucial role in the overall performance of the cryptographic processor. Hence, better results can be obtained by designing efficient arithmetic modules such as modular addition, multiplication, exponentiation and squaring. This thesis is organized into three papers, describes the efficient implementation of modular arithmetic units, application of these modules in International Data Encryption Algorithm (IDEA). Second paper describes the IDEA algorithm implementation using the existing techniques and using the proposed efficient modular units. The third paper describes the fault tolerant design of a modular unit which has online self-checking capability --Abstract, page iv

A Comprehensive Fault Model for Concurrent Error Detection in MOS Circuits

Naval Electronics Sys. Comm. and Office of Naval Research / N00039-80-C-0556Ope

5G NR-밴드 무선 주파수 송수신기의 검증을 위한 모델링 방법

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2021.8. 김재하.도래한 초연결시대에서는 스마트폰뿐만 아니라 다양한 사물 인터넷 디바이스들이 5세대 이동통신 시스템을 활용하면서, 늘어난 데이터량과 트래픽을 감당하기 위해 밀리미터파 대역의 사용이 필수적일 것이다. 시스템이 보다 대용량화 그리고 광대역화 됨에 따라, 통신 규약을 만족시키기 위해, 점차 거대한 디지털 캘리브레이션 및 신호처리 로직이, 무선 통신 전단부 칩에 함께 집적되고 있다. 따라서 멀티-도메인의 신호(아날로그/디지털/무선통신 신호)가 복잡하게 혼성된 무선통신 집적회로 칩을, 짧은 개발 기간 동안 충분히 검증하기엔 어려움이 따른다. 일반적으로 혼성 신호 시스템을 검증하기 위해서는, 하위 시스템을 모두 포함해서 시간 도메인의 시뮬레이션을 수행해야 하는데, 이를 위한 스파이스와 스파이스-하드웨어 기술 언어의 co-시뮬레이션은 지나치게 느리다는 한계가 있기 때문이다. 따라서, 멀티-도메인의 신호를 빠르고 정확하게 시뮬레이션 가능하게 하는 모델링 방법과, 다양한 시나리오의 검증 완성도를 향상시켜줄 있는 검증 기술이 모두 요구된다. 혼성 시스템을 검증하기 위해서는, 아날로그와 무선 통신 블록들을 시스템 베릴로그 상에서 구현된 함수적 모델로 대체하고, 디지털 블록들과 함께 하나의 디지털 플랫폼에서 시뮬레이션하는 것이 효과적이다. 실제 설계할 때, 문제가 되는 대부분의 에러들은, 연결 오류, 부호 오류, 신호 순서 오류, 혹은 잘못된 파워 도메인과의 연결과 같이 사소한 오류들이다. 이러한 오류를 찾기 위해, 오래 걸리는 트랜지스터-레벨의 시뮬레이션을 수행하기보다는, 아날로그 스파이스 모델들을 시스템 베릴로그 모델들로 대체하고, 보다 다양한 시나리오를 빠르게 검증하는 방법이 검증 완성도를 향상시키는데 적합하다. 그럼에도, 지나치게 단순한 선형 모델이나, 중요한 회로 특성이 빠진 모델로는 원하는 수준의 검증이 불가능할 수 있다. 예를 들어, 직접 변조 구조의 무선통신 송수신기에서 발생하는 비이상 효과, 저전력 동작을 하면서 발생하는 비선형 효과, 그리고 흔히 메모리 효과는 모델에 효과를 충분히 반영해 주어야만, 주파수 도메인에서의 검증, 성능 예측 등의 검증을 의미 있게 수행할 수 있다. 문제는 비선형 시스템은 훨씬 복잡한 식으로 표현되며, 시뮬레이션 시 연산량도 크게 늘어나기 때문에, 비선형 모델을 만들고 시뮬레이션 하기가 쉽지 않다는 것이다. 따라서 모델이 비이상성들을 충분히 반영하면서도 효과적인 검증을 가능하게 하는 모델링/시뮬레이션 방법 역시 요구된다. 본 학위 논문에서는, 무선통신 송수신기 집적회로 전체의 모사 모델을 제안한다. 모델은 누설 신호와 신호 간 불일치에 의한 비-이상적인 효과를 엑스모델의 알고리즘을 활용해 반영하였고, 비선형성과 메모리 효과를 볼테라-섭동법을 활용해 반영하였다. 제안하는 모델은 다양한 주파수 대역과 동작 모드를 검증하는데, 기존 등가 베이스밴드 모델보다 30~1800배 빠르게 시뮬레이션 할 수 있었고, 비이상 효과에 대해, 통신 성능들(심볼의 오류 벡터의 크기, 인접 채널의 파워 그리고 비트 에러)을 평가 가능했다. 나아가, 아날로그 검사기를 활용한 기능 검증법과 모델 파라미터 커버리지 분석법을 적용하여, 시스템-레벨 검증의 완성도를 향상시켰다. 무선통신 집적회로 모델에 다양한 디자인/파라미터 오류를 주입하고, 시뮬레이션 동안 검사기가 찾은 에러의 개수와 커버리지 결과를 실험적으로 보였다.In mobile RF transceiver systems, the large number of digital circuits employed to compensate or calibrate the non-idealities of the RF circuits call for models that can work within the digital verification platform, such as SystemVerilog. While baseband-equivalent real-number models (RNMs) are the current state-of-the-art for modeling RF transceivers in SystemVerilog, their simulation speeds and accuracy are not adequate predicting performance degradation. Since, its signals can only model the frequency components near the carrier frequency but not the DC offsets or high-order harmonic effects arising due to nonlinearities. Therefore, the growing impacts of nonlinearities call for nonlinear modeling of their key components to predict the overall system's performance. This dissertation presents the models for a multi-standard, direct-conversion RF transceiver for evaluating its system-level performance and verifying its digital controllers. Also, this work demonstrates the Volterra series model for the nonlinear analysis of a low-noise amplifier circuit in SystemVerilog, leveraging the functional expression and event-driven simulation capability of XMODEL. The simulation results indicate that the presented models, including the digital configuration/calibration logic for the 5G sub-6GHz-band and mmWave-band transceiver, can deliver 30–1800× higher speeds than the baseband-equivalent RNMs while estimating the quadrature amplitude modulation signal constellation and error vector magnitude in the presence of non-idealities such as nonlinearities, DC offsets, and I/Q imbalances. In addition, it implements functionality checkers and parameter coverage analysis to advance the completeness of system-level verification of the RF transceivers model.Chapter 1. Introduction 1 1.1 Design and Verification Flow . 1.2 5G NR Band RF Transceiver IC . 1.3 Baseband-Equivalent and Passband Modeling . 1.4 Thesis Organization . Chapter 2. Modeling and Simulation of RF Transceiver 11 2.1 Direct Conversion RF Transceiver . 2.2 Proposed Transceiver Models . 2.3 System and Simulation Performance . Chapter 3. Nonlinear RF System Modeling 28 3.1 Volterra / Perturbation Method . 3.2 Low Noise Amplifier Example . 3.3 Nonlinearity Analysis . Chapter 4. Coverage Analysis and Functional Verification 42 4.1 Model Parameter Coverage Analysis . 4.2 Self-Checking Testbench . Chapter 5. Conclusion 54 Appendix 55 A.1 Trigonometric Equation for Non-Ideal Effects . A.2 RNM Baseband Equivalent Modeling . A.3 Parameter Coverage Analysis . A.4 List of Models . Bibliography 63 Abstract in Korean 66석

LSI/VLSI design for testability analysis and general approach

The incorporation of testability characteristics into large scale digital design is not only necessary for, but also pertinent to effective device testing and enhancement of device reliability. There are at least three major DFT techniques, namely, the self checking, the LSSD, and the partitioning techniques, each of which can be incorporated into a logic design to achieve a specific set of testability and reliability requirements. Detailed analysis of the design theory, implementation, fault coverage, hardware requirements, application limitations, etc., of each of these techniques are also presented

Dependable Computing on Inexact Hardware through Anomaly Detection.

Reliability of transistors is on the decline as transistors continue to shrink in size. Aggressive voltage scaling is making the problem even worse. Scaled-down transistors are more susceptible to transient faults as well as permanent in-field hardware failures. In order to continue to reap the benefits of technology scaling, it has become imperative to tackle the challenges risen due to the decreasing reliability of devices for the mainstream commodity market. Along with the worsening reliability, achieving energy efficiency and performance improvement by scaling is increasingly providing diminishing marginal returns. More than any other time in history, the semiconductor industry faces the crossroad of unreliability and the need to improve energy efficiency. These challenges of technology scaling can be tackled by categorizing the target applications in the following two categories: traditional applications that have relatively strict correctness requirement on outputs and emerging class of soft applications, from various domains such as multimedia, machine learning, and computer vision, that are inherently inaccuracy tolerant to a certain degree. Traditional applications can be protected against hardware failures by low-cost detection and protection methods while soft applications can trade off quality of outputs to achieve better performance or energy efficiency. For traditional applications, I propose an efficient, software-only application analysis and transformation solution to detect data and control flow transient faults. The intelligence of the data flow solution lies in the use of dynamic application information such as control flow, memory and value profiling. The control flow protection technique achieves its efficiency by simplifying signature calculations in each basic block and by performing checking at a coarse-grain level. For soft applications, I develop a quality control technique. The quality control technique employs continuous, light-weight checkers to ensure that the approximation is controlled and application output is acceptable. Overall, I show that the use of low-cost checkers to produce dependable results on commodity systems---constructed from inexact hardware components---is efficient and practical.PhDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113341/1/dskhudia_1.pd

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

Robust design of deep-submicron digital circuits

Avec l'augmentation de la probabilité de fautes dans les circuits numériques, les systèmes développés pour les environnements critiques comme les centrales nucléaires, les avions et les applications spatiales doivent être certifies selon des normes industrielles. Cette thèse est un résultat d'une cooperation CIFRE entre l'entreprise Électricité de France (EDF) R&D et Télécom Paristech. EDF est l'un des plus gros producteurs d'énergie au monde et possède de nombreuses centrales nucléaires. Les systèmes de contrôle-commande utilisé dans les centrales sont basés sur des dispositifs électroniques, qui doivent être certifiés selon des normes industrielles comme la CEI 62566, la CEI 60987 et la CEI 61513 à cause de la criticité de l'environnement nucléaire. En particulier, l'utilisation des dispositifs programmables comme les FPGAs peut être considérée comme un défi du fait que la fonctionnalité du dispositif est définie par le concepteur seulement après sa conception physique. Le travail présenté dans ce mémoire porte sur la conception de nouvelles méthodes d'analyse de la fiabilité aussi bien que des méthodes d'amélioration de la fiabilité d'un circuit numérique.The design of circuits to operate at critical environments, such as those used in control-command systems at nuclear power plants, is becoming a great challenge with the technology scaling. These circuits have to pass through a number of tests and analysis procedures in order to be qualified to operate. In case of nuclear power plants, safety is considered as a very high priority constraint, and circuits designed to operate under such critical environment must be in accordance with several technical standards such as the IEC 62566, the IEC 60987, and the IEC 61513. In such standards, reliability is treated as a main consideration, and methods to analyze and improve the circuit reliability are highly required. The present dissertation introduces some methods to analyze and to improve the reliability of circuits in order to facilitate their qualification according to the aforementioned technical standards. Concerning reliability analysis, we first present a fault-injection based tool used to assess the reliability of digital circuits. Next, we introduce a method to evaluate the reliability of circuits taking into account the ability of a given application to tolerate errors. Concerning reliability improvement techniques, first two different strategies to selectively harden a circuit are proposed. Finally, a method to automatically partition a TMR design based on a given reliability requirement is introduced.PARIS-Télécom ParisTech (751132302) / SudocSudocFranceF