A survey on scheduling and mapping techniques in 3D Network-on-chip

Network-on-Chips (NoCs) have been widely employed in the design of multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs enable communications between on-chip Intellectual Property (IP) cores and allow those cores to achieve higher performance by outsourcing their communication tasks. Mapping and Scheduling methodologies are key elements in assigning application tasks, allocating the tasks to the IPs, and organising communication among them to achieve some specified objectives. The goal of this paper is to present a detailed state-of-the-art of research in the field of mapping and scheduling of applications on 3D NoC, classifying the works based on several dimensions and giving some potential research directions

Design and Implementation of High QoS 3D-NoC using Modified Double Particle Swarm Optimization on FPGA

One technique to overcome the exponential growth bottleneck is to increase the number of cores on a processor, although having too many cores might cause issues including chip overheating and communication blockage. The problem of the communication bottleneck on the chip is presently effectively resolved by networks-on-chip (NoC). A 3D stack of chips is now possible, thanks to recent developments in IC manufacturing techniques, enabling to reduce of chip area while increasing chip throughput and reducing power consumption. The automated process associated with mapping applications to form three-dimensional NoC architectures is a significant new path in 3D NoC research. This work proposes a 3D NoC partitioning approach that can identify the 3D NoC region that has to be mapped. A double particle swarm optimization (DPSO) inspired algorithmic technique, which may combine the characteristics having neighbourhood search and genetic architectures, also addresses the challenge of a particle swarm algorithm descending into local optimal solutions. Experimental evidence supports the claim that this hybrid optimization algorithm based on Double Particle Swarm Optimisation outperforms the conventional heuristic technique in terms of output rate and loss in energy. The findings demonstrate that in a network of the same size, the newly introduced router delivers the lowest loss on the longest path.  Three factors, namely energy, latency or delay, and throughput, are compared between the suggested 3D mesh ONoC and its 2D version. When comparing power consumption between 3D ONoC and its electronic and 2D equivalents, which both have 512 IP cores, it may save roughly 79.9% of the energy used by the electronic counterpart and 24.3% of the energy used by the latter. The network efficiency of the 3D mesh ONoC is simulated by DPSO in a variety of configurations. The outcomes also demonstrate an increase in performance over the 2D ONoC. As a flexible communication solution, Network-On-Chips (NoCs) have been frequently employed in the development of multiprocessor system-on-chips (MPSoCs). By outsourcing their communication activities, NoCs permit on-chip Intellectual Property (IP) cores to communicate with one another and function at a better level. The important components in assigning application duties, distributing the work to the IPs, and coordinating communication among them are mapping and scheduling methods. This study aims to present an entirely advanced form of research in the area of 3D NoC mapping and scheduling applications, grouping the results according to various parameters and offering several suggestions for further research

Design and implementation of a subject identification system based on Electroencephalogram

Biometrics are essential methods of identifying people nowadays. There are many types of biometrics, such as the classic methods for iris, face and fingerprint; but most of these are not robust or secure. Recently, biometrics based on electroencephalogram signals using machine learning algorithms have proven to be one of the highest quality and robust methods. Electroencephalograms have advantages over traditional modalities as they are extremely difficult to reproduce and cannot be captured stealthily from a distance. This work describes a system capable of acquiring real-time electroencephalogram signals, processing them using the PREP pipeline, to clean them and improve performance, and making subject identity predictions from electroencephalogram signals using different artificial intelligence algorithms. The system is portable, robust, low-cost and connected to the network to send the results to a server. It is composed of an acquisition system using an analog-to-digital converter and protection systems for electroencephalogram signals. The system is based on a Raspberry Pi Zero 2W as the computer in charge of performing all the computational work of the artificial intelligence algorithms and managing the different tasks. Several deep learning algorithms have been used and compared in terms of results and performance. The EEGNet model has provided the best results with an accuracy of 86.74% in its predictions. The data input to the model has been preprocessed with the PREP pipeline, which has proven to be effective in the results, as it improves the performance of all models that use it. The system provides a functional device with outstanding results that leads the way for future work and applications

Location estimation in a 3D environment using radio frequency identification tags

RFID tag location estimation in a 3D environment is investigated. The location of the tag with unknown coordinates can be estimated with certain accuracy. However, accuracy can be improved using the knowledge based on measurement of additional reference tags with known location. This thesis studies the mathematical formulation and practical realization of location sensing using RFID tags. Deviating from the standard use of RFID technology which employs one tag reader to identify the presence of tag, here multiple tag readers with known location are used to estimate the physical location of an individual tag, with/without the help of few reference tags with known locations. Mathematical model of this concept has been developed based on distance variations in terms of signal strength. Experimental approach with limited range passive tags has been carried out. Since the range of the RFID system was limited only to a few inches, signal strength variations were insignificant. Instead, time domain measurements with the help of an external antenna were conducted. The composite signal width including of the wake up signal of the interrogator, travel time between the interrogator and tag, and the tag\u27s response was measured and quantified. It was observed that the width of the signal was proportional to the distance between the tag reader and the tag. It was noticed that the use of four RFID tag readers yielded fairly accurate results to identify the location the tag based on the mathematical formulation developed here. Additionally, concept of trilateration has also been extended for tracking the tag of unknown location without the use of reference tags. Archival data set corresponding to all tag location due to four different tag readers was compiled. The unknown tag was probed with four tag readers and matching the data to the archival data set yielded unique and accurate results for its unknown location. It was demonstrated that both approaches were proved to be cost-effective techniques and estimation of the location of a specific tag has been achieved with sufficient accuracy

On Energy Efficient Computing Platforms

In accordance with the Moore's law, the increasing number of on-chip integrated transistors has enabled modern computing platforms with not only higher processing power but also more affordable prices. As a result, these platforms, including portable devices, work stations and data centres, are becoming an inevitable part of the human society. However, with the demand for portability and raising cost of power, energy efficiency has emerged to be a major concern for modern computing platforms. As the complexity of on-chip systems increases, Network-on-Chip (NoC) has been proved as an efficient communication architecture which can further improve system performances and scalability while reducing the design cost. Therefore, in this thesis, we study and propose energy optimization approaches based on NoC architecture, with special focuses on the following aspects. As the architectural trend of future computing platforms, 3D systems have many bene ts including higher integration density, smaller footprint, heterogeneous integration, etc. Moreover, 3D technology can signi cantly improve the network communication and effectively avoid long wirings, and therefore, provide higher system performance and energy efficiency. With the dynamic nature of on-chip communication in large scale NoC based systems, run-time system optimization is of crucial importance in order to achieve higher system reliability and essentially energy efficiency. In this thesis, we propose an agent based system design approach where agents are on-chip components which monitor and control system parameters such as supply voltage, operating frequency, etc. With this approach, we have analysed the implementation alternatives for dynamic voltage and frequency scaling and power gating techniques at different granularity, which reduce both dynamic and leakage energy consumption. Topologies, being one of the key factors for NoCs, are also explored for energy saving purpose. A Honeycomb NoC architecture is proposed in this thesis with turn-model based deadlock-free routing algorithms. Our analysis and simulation based evaluation show that Honeycomb NoCs outperform their Mesh based counterparts in terms of network cost, system performance as well as energy efficiency.Siirretty Doriast

Addressing Manufacturing Challenges in NoC-based ULSI Designs

Hernández Luz, C. (2012). Addressing Manufacturing Challenges in NoC-based ULSI Designs [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/1669

Artificial Neural Networks (ANNs) for Spectral Interference Correction Using a Large-Size Spectrometer and ANN-Based Deep Learning for a Miniature One

Artificial neural networks (ANNs) are evaluated for spectral interference correction using simulated and experimentally obtained spectral scans. Using the same data set (where possible), the predictive ability of shallow depth ANNs was validated against partial least squares (PLS, a traditional chemometrics method). Spectral interference (in the form of overlaps between spectral lines) is a key problem in large-size, long focal length inductively coupled plasma-optical emission spectrometry (ICP-OES). Unless corrected, spectral interference can be sufficiently severe to the point of preventing precise and accurate analytical determinations. In miniaturized, microplasma-based optical emission spectrometry with a portable, short focal length spectrometer (having poorer resolution than its large-size counterpart), spectral interference becomes even more severe. To correct it, we are evaluating use of deep learning ANNs. Details are provided in this chapter