Emerging cad and bim trends in the aec education: An analysis from students\u27 perspective

As the construction industry is moving towards collaborative design and construction practices globally, training the architecture, engineering, and construction (AEC) students professionally related to CAD and BIM became a necessity rather than an option. The advancement in the industry has led to collaborative modelling environments, such as building information modelling (BIM), as an alternative to computer-aided design (CAD) drafting. Educators have shown interest in integrating BIM into the AEC curriculum, where teaching CAD and BIM simultaneously became a challenge due to the differences of two systems. One of the major challenges was to find the appropriate teaching techniques, as educators were unaware of the AEC students’ learning path in CAD and BIM. In order to make sure students learn and benefit from both CAD and BIM, the learning path should be revealed from students’ perspective. This paper summarizes the background and differences of CAD and BIM education, and how the transition from CAD to BIM can be achieved for collaborative working practices. The analysis was performed on freshman and junior level courses to learn the perception of students about CAD and BIM education. A dual-track survey was used to collect responses from AEC students in four consecutive years. The results showed that students prefer BIM to CAD in terms of the friendliness of the user-interface, help functions, and self-detection of mistakes. The survey also revealed that most of the students believed in the need for a BIM specialty course with Construction Management (CM), Structure, and Mechanical-Electrical-Plumbing (MEP) areas. The benefits and challenges of both CAD and BIM-based software from students’ perspectives helps to improve the learning outcomes of CAD/BIM courses to better help students in their learning process, and works as a guideline for educators on how to design and teach CAD/BIM courses simultaneously by considering the learning process and perspectives of students. © 2018 The autho

Network emulation focusing on QoS-Oriented satellite communication

This chapter proposes network emulation basics and a complete case study of QoS-oriented Satellite Communication

Using the Proteus virtual environment to train future IT professionals

Abstract. Based on literature review it was established that the use of augmented reality as an innovative technology of student training occurs in following directions: 3D image rendering; recognition and marking of real objects; interaction of a virtual object with a person in real time. The main advantages of using AR and VR in the educational process are highlighted: clarity, ability to simulate processes and phenomena, integration of educational disciplines, building an open education system, increasing motivation for learning, etc. It has been found that in the field of physical process modelling the Proteus Physics Laboratory is a popular example of augmented reality. Using the Proteus environment allows to visualize the functioning of the functional nodes of the computing system at the micro level. This is especially important for programming systems with limited resources, such as microcontrollers in the process of training future IT professionals. Experiment took place at Borys Grinchenko Kyiv University and Sumy State Pedagogical University named after A. S. Makarenko with students majoring in Computer Science (field of knowledge is Secondary Education (Informatics)). It was found that computer modelling has a positive effect on mastering the basics of microelectronics. The ways of further scientific researches for grounding, development and experimental verification of forms, methods and augmented reality, and can be used in the professional training of future IT specialists are outlined in the article

Micro-threading and FPGA implementation of a RISC microprocessor : a thesis presented in partial fulfilment of the requirements for the degree of Master of Science in Computer Science at Massey University, Palmerston North, New Zealand

Appendix E removed due to copyright restrictions. Articles are available in the print copy held in the libraryThis thesis is the outcome of research in two areas of computer technology: microprocessor and multi-processor architectures (specifically from the perspective of how differently they tolerate highly-latent and non-deterministic events), and hardware design of complex digital systems containing both datapath and control (particularly microprocessors). This thesis starts by pointing out that in order to achieve high processing speeds, current popular superscalar microprocessors (e.g. Intel Pentiums, Digital Alpha, etc) rely heavily on the technique of speculating the outcome of instruction flow in order to predict the behaviour of non-deterministic computing operations (as in loading operands from high-latency memory into the processor). This is fine only if the speculation is correct. But, what if it isn't? If the speculation fails, this would mean that the processor has to abandon its current decision (which now proved to be the wrong one) for the instruction flow path taken and to start all over again with the other path (the actual correct one). This is a waste of valuable processing time and hardware resources and a reduction of performance when speculation fails. Therefore, these processors can achieve high performance only when the majority of speculations are successful (being able to predict the right path). In an attempt to overcome the above shortcomings, the first part of this thesis is an investigation of the novel vector micro-threading architecture as an alternative approach to the current superscalar-based speculative microprocessor designs. Micro-threading is based on the not-so-novel multithreading technique, which avoids speculation altogether and instead, starts running a different thread of instructions while waiting for the non-determinism to be resolved. This utilizes the chip resources more efficiently without waste of any processing power. The rest of this thesis focuses on the baseline RISC processor platform, the MIPS R2000, which is reviewed first then partially synthesized from the RTL (Register Transfer Level) description using VHDL and then simulated and tested. This is conducted in order for future research to build upon and add the micro-threading architectural add-ons and modifications. Keywords: Micro-threading, Latency Tolerance, FPGA Synthesis, RISC Architecture, MIPS R2000 processor, VHDL

An Experimental Microarchitecture for a Superconducting Quantum Processor

Quantum computers promise to solve certain problems that are intractable for classical computers, such as factoring large numbers and simulating quantum systems. To date, research in quantum computer engineering has focused primarily at opposite ends of the required system stack: devising high-level programming languages and compilers to describe and optimize quantum algorithms, and building reliable low-level quantum hardware. Relatively little attention has been given to using the compiler output to fully control the operations on experimental quantum processors. Bridging this gap, we propose and build a prototype of a flexible control microarchitecture supporting quantum-classical mixed code for a superconducting quantum processor. The microarchitecture is based on three core elements: (i) a codeword-based event control scheme, (ii) queue-based precise event timing control, and (iii) a flexible multilevel instruction decoding mechanism for control. We design a set of quantum microinstructions that allows flexible control of quantum operations with precise timing. We demonstrate the microarchitecture and microinstruction set by performing a standard gate-characterization experiment on a transmon qubit.Comment: 13 pages including reference. 9 figure