797 research outputs found
Design and Characterization of a Secure Automatic Dependent Surveillance-Broadcast Prototype
During sensitive military operations, such as air operations in theater, the broadcasting of ADS-B messages poses a serious security concern, but the small message payload of ADS-B transmissions renders encryption standards such as AES unsuitable. Format-preserving encryption (FPE), a technique already in use on small message sizes such as credit card numbers, provides a suitable implementation of strong symmetric key encryption for the military context. This research proposes and details a Secure ADS-B (SADS-B) system which utilizes a bump-in-the-wire approach for encryption and decryption of ADS-B messages using FPE, going on to then characterize the prototype\u27s performance using the following metrics: detection and error rates, operational latency, and utilization of resources on the underlying field programmable gate array (FPGA) hardware. Findings include sub-millisecond operational latency, full data rate throughput capability for ADS-B, and approximately 50% utilization of the available FPGA resources. Overall, findings suggest that a layered security system such as SADS-B is suitable for adding confidentiality to ADS-B
Implementation of a Symmetric Chaotic Encryption Scheme
Voice over Internet Protocol technology (VoIP) is progressing commendably, but packet
loss, propagation delay, jitter, unreliable IP networks, and vulnerability to attacks by
Internet hackers are among critical issues that have been identified. Voice privacy and
security needs to focused upon and data encryption techniques are the answers in
providing the security needed. However, traditional cryptosystems demand high
computational complexity andhigh digital signal processors which in return increases the
cost of implementation.
There is parallel growth in cryptographic techniques which originated anintense research
activity and the search for new directions in cryptography such as chaotic encryption.
Due to its deterministic nature and its sensitivity to initial conditions, chaos has a certain
potential in creating a newway of securing information to be transmitted or stored.
There are two main objectives to this project. First is study the feasibility of the chaotic
encryption scheme in providing a solution in to preserve data security while maintaining
the voice quality for voice over Internet Protocol. Secondly, a new scheme based on a
chaos system will be implemented for voice data. In order to achieve the second
objective, a study had been carried out on other proposed schemes mainly the
Hierarchical Data Security Protection (HDSP) for VoIP. This scheme performs two main
operations which is the data-frame interleaving and intra-frame data encryption using bit
swapping. Based onthe HDSP scheme, the author suggests a new scheme using two level
encryption techniques, based on chaos. In this scheme, the author uses the bit swapping
technique as the second encryption-decryption level and enhances it with a first level
encryption-decryption scheme using the two's compliment overflow nonlinearity
encoder-decoder pair.
The implementation ofthis scheme is specified to do real time processing ofvoice data. It
can also be used to read, encrypt and write a wave file. The entire system is implemented,
tested and validated using MATLAB and Visual C++.
Due to the promising prospect ofchaotic encryption in the field ofcryptography, and the
lack ofimplementation ofthis new encryption-decryption algorithm, this project focuses
on introducing a new symmetric encryption-decryption scheme based on a chaos system
for VoIP
OPTIMIZATION OFADVANCEDENCRYPTION STANDARD (AES) IN FPGA IMPLEMENTATION USING S-BOX INTEGRATION
Cryptography has a significant role in the security of data transmission. The
algorithm of Rijndael was selected and adopted by National Institute of Standards
and Technology (NIST) U.S. as Advanced Encryption Standard (AES) in October
2000, in order to replace the old Data Encryption Standard (DES).
As compared to software, hardware implementations provide more physical security
as well as faster speed. Thus, in this project, the AES cryptograph was simulated
with FPGA, by using Verilog HDL. The main objectives are the architectural and
algorithmic optimizations of the AES implementation, which would in turn benefit
applications that are both speed and area critical.
The optimization methodology in this project was achieved using S-Box integration.
S-Box, which is for SubBytes, and Inverse S-Box, which is for InvSubBytes, are both
constituted of two 256-byte substitution tables. In fact, it is usual that in any high
speed full pipelining AES implementations, it would require 24 S-Box tables and 16
InverseS-Box tables at any one time.
Nonetheless, mathematical formulas show that S-Box and Inverse S-Box could
actually beachieved with only g,fand/1. Multiplicative inverse, org, is a 256-byte
look-up table. On the other hand, affine transformation,/, and its inverse,/7, can be
implemented with a limited number of XOR gates. Accordingly, the number of
substitution tables necessitated could be reduced by half.
Consequently, the new implementation would still obtain the identical S-Box and
Inverse S-Box values, but merely from one look-up table and some simple logic
gates. The new design shows that it can deliver a throughput of 203 Mbit/sec with
hardware of 78,977 gate counts. Hardware complexity is reduced to 69% of its
originalwhile still able to function at core process of only 12 cycles
Method and system for spatial data input, manipulation and distribution via an adaptive wireless transceiver
A method and system for spatial data manipulation input and distribution via an adaptive wireless transceiver. The method and system include a wireless transceiver for automatically and adaptively controlling wireless transmissions using a Waveform-DNA method. The wireless transceiver can operate simultaneously over both the short and long distances. The wireless transceiver is automatically adaptive and wireless devices can send and receive wireless digital and analog data from various sources rapidly in real-time via available networks and network services
Barrel Shifter Physical Unclonable Function Based Encryption
Physical Unclonable Functions (PUFs) are circuits designed to extract
physical randomness from the underlying circuit. This randomness depends on the
manufacturing process. It differs for each device enabling chip-level
authentication and key generation applications. We present a protocol utilizing
a PUF for secure data transmission. Parties each have a PUF used for encryption
and decryption; this is facilitated by constraining the PUF to be commutative.
This framework is evaluated with a primitive permutation network - a barrel
shifter. Physical randomness is derived from the delay of different shift
paths. Barrel shifter (BS) PUF captures the delay of different shift paths.
This delay is entangled with message bits before they are sent across an
insecure channel. BS-PUF is implemented using transmission gates; their
characteristics ensure same-chip reproducibility, a necessary property of PUFs.
Post-layout simulations of a common centroid layout 8-level barrel shifter in
0.13 {\mu}m technology assess uniqueness, stability and randomness properties.
BS-PUFs pass all selected NIST statistical randomness tests. Stability similar
to Ring Oscillator (RO) PUFs under environment variation is shown. Logistic
regression of 100,000 plaintext-ciphertext pairs (PCPs) failed to successfully
model BS- PUF behavior
Customisable arithmetic hardware designs
Imperial Users onl
FPGA based secure and noiseless image transmission using LEA and optimized bilateral filter
In today’s world, the transmission of secured and noiseless image is a difficult task. Therefore, effective strategies are important to secure the data or secret image from the attackers. Besides, denoising approaches are important to obtain noise-free images. For this, an effective crypto-steganography method based on Lightweight Encryption Algorithm (LEA) and Modified Least Significant Bit (MLSB) method for secured transmission is proposed. Moreover, a bilateral filter-based Whale Optimization Algorithm (WOA) is used for image denoising. Before image transmission, the secret image is encrypted by the LEA algorithm and embedded into the cover image using Discrete Wavelet Transform (DWT) and MLSB technique. After the image transmission, the extraction process is performed to recover the secret image. Finally, a bilateral filter-WOA is used to remove the noise from the secret image. The Verilog code for the proposed model is designed and simulated in Xilinx software. Finally, the simulation results show that the proposed filtering technique has superior performance than conventional bilateral filter and Gaussian filter in terms of Peak Signal to Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM)
Functional verification framework of an AES encryption module
Over the time, the development of the digital design has increased dramatically and nowadays many different circuits and systems are designed for multiple purposes in short time lapses. However, this development has not been based only in the enhancement of the design tools, but also in the improvement of the verification tools, due to the outstanding role of the verification process that certifies the adequate performance and the fulfillment of the requirements. In the verification industry, robust methodologies such as the Universal Verification Methodology (UVM) are used, an example of this is [1], but they have not been implemented yet in countries such as Peru and they seem inconvenient for educational purposes. This research propose an alternative methodology for the verification process of designs at the industry scale with a modular structure that contributes to the development of more complex and elaborated designs in countries with little or none verification background and limited verification tools. This methodology is a functional verification methodology described in SystemVerilog and its effectiveness is evaluated in the verification of an AES (Advance Encryption Standard) encryption module obtained from [2]. The verification framework is based on a verification plan (developed in this research as well) with high quality standards as it is defined in the industry. This verification plan evaluates synchronization, data validity, signal stability, signal timing and behavior consistency using Assertions, functional coverage and code coverage. An analysis of the outcomes obtained shows that the AES encryption module was completely verified obtaining 100% of the Assertions evaluation, 100% of functional verification and over 95% of code coverage in all approaches (fsm, block, expression, toggle). Besides, the modular structure defines the intercommunication with the Design only in the bottom most level, which facilitates the reuse of the verification framework with different bus interfaces. Nonetheless, this unit level verification framework can be easily instantiated by a system level verification facilitating the scalability. Finally, the documentation, tutorials and verification plan templates were generated successfully and are aimed to the development of future projects in the GuE PUCP (Research group in Microelectronics). In conclusion, the methodology proposed for the verification framework of the AES encryption module is in fact capable of verifying designs at the industry scale with high level of reliability, defining a very detailed and standardized verification plan and containing a suitable structure for reuse and scalability.Tesi
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