Computer Simulation and Device Physics of SiGe Heterojunction Bipolar Transistors

Recent advances in semiconductor growth technology have enabled the growth of SiGe strained layers on silicon substrates. Si/SiGe technology has a promising future, especially in microwave HBT applications. This work describes the development of an existing two-dimensional drift-diffusion device simulation program for accurate modelling of SiGe heterojunction bipolar transistors (HBT\u27s). PUPHS2D (Purdue University Program for Heterostructure Simulation in Two Dimensions) was formulated by Paul Dodd [Dod89] as an AlGaAs/GaAs HBT simulation tool. This work describes the extension of this program to the silicon and Si 1|_xGex material systems. The computer model allows the user to explore internal device physics as well as terminal characteristics of a device. Field-dependent mobility has been added to the program in order to more accurately compute high-field transport phenomena. The simulation tool is used to study the performance of silicon bipolar transistors and Si/SiGe HBT\u27s, and these results are presented in chapter 4

Process development and device modelling of gallium arsenide heterojunction bipolar transistors

This thesis discusses the processing and analysis of high speed semiconductor devices with emphasis on GaAs-based heterojunction bipolar transistors. The heterojunction transistor process is developed as an essential part of this thesis. Device physics is first reviewed in depth to construct a solid basis for physical one dimensional simulation of heterojunction bipolar junction transistors. Theory is then applied to a simulation platform in a way which facilitates device design and evaluation at practical level. The simulation platform was used in designing epitaxial layers for a transistor structure with heavily doped base layer and current gain target at 50. The developed transistor process relies on wet chemical isolation etching, and takes into account the restrictions that arise from the academic perspective of the processing environment. The process development goal was educational robustness. The development effort for HBT process is explained in detail, and processing steps are illustrated with scanning electron microscope images. The most critical processing steps were for defining isolation depths. Isolation is based on slow citric acid wet chemical etching monitored with a high precision profilometer. Active devices form isolated hills or "mesas" on the semi-insulating substrate. Because of the rather tall etched structures the lithography is of planarizing type. The process includes a unique double layer planarising lithography for AZ 5214E resist, developed within the framework of this thesis. The lithography is doubly functional such that it also allows two resist layers to be patterned separately on top of each other, which is utilised in defining shallow air bridges in the transistor structures. The most important measurement results are explained. Degradation of transistor performance after excessive heating or current stress is also demonstrated, and a method for processing devices with minimal amount of heating is introduced as a means to tackle the problem. Measured collector characteristics of various types of HBTs are given. Best DC characteristics were achieved with a transistor structure including non-alloyed contacts and Schottky diode collector. This thesis focused on process development and DC analysis of the transistor. Frequency characteristics were measured only for completeness. It is shown that even the non-optimized process was capable of producing transistors with power gain cut off frequency exceeding 1 GHz.reviewe

Characteristics of UHF transistors using autoregistered structures

The basis of a novel bipolar transistor structure was proposed by Dr R. Aubusson of Middlesex Polytechnic in 1977. The novelty lies in replacing the conventional overlay transistor's P+ base grid with a refractory metal grid, in order (a) to lower the base resistance and (b) to autoregister the emitter. It was claimed that the linearity of the transistor would also be improved. A number of questions raised by this idea have been investigated, the methods and conclusions of which are presented here. Plausible structures, using the metal base grid, are proposed and compared with conventional structures. Some advantages are seen to be possible. The current understanding of distortion analysis applied to transistors is reviewed. The main ideas are presented in a unified manner and are extended to higher order. A number of the transistor's second order effects are analysed in a novel fashion. The metal base grid transistor is analysed and compared with conventional transistors, with favourable results. Practical aspects of fabricating the metal base grid transistor were investigated. A procedure for deposition has been determined and is presented here along with the film physical and electrical characteristics. Analysis of the tungsten-silicon interface shows the suitability of the metallization as a base grid. Suitable means of delineating the tungsten film have been assessed and a working procedure determined. Subsequent deposition of various insulators has been investigated and the problems associated with the readily oxidized tungsten film have been overcome. Formation of the emitter, requiring further high temperature processing, has been assessed in view of the limitations imposed by the preformed base metallization. In summary, it has been shown that the novel structure can be constructed and that significant performance improvement is to be expected, although a full realization was not possible within the resource constraints of the project

Transport models and advanced numerical simulation of silicon-germanium heterojunction bipolar transistors

Applications in the emerging high-frequency markets for millimeter wave applications more and more use SiGe components for cost reasons. To support the technology effort, a reliable TCAD platform is required. The main issue in the simulation of scaled devices is related to the limitations of the physical models used to describe charge carrier transport. Inherent approximations in the HD formalism are discussed over different technology nodes, providing for the first time a complete survey of HD models capability and restrictions with scaling for simulation of SiGe HBTs. Moreover, a complete set of models for transport parameters of SiGe HBTs is reported, including low-field mobility, energy relaxation time, saturation velocity, high-field mobility and effective density of state. Implementation in a commercial device simulator is drawn and findings are compared with simulation results obtained using a standard set of models and with trustworthy results (i.e. MC and SHE simulation results and experimental data), validating proposed models and clarifying their reliability and accuracy over different technologies. Finally, electrical breakdown phenomena in SiGe HBTs are analyzed: a novel complete model for multiplication factor is reported and validated by experimental results; new M model provides an exhaustive accuracy over a wide range of collector voltages

Process technology for High Speed InP Based Heterojunction Bipolar Transistors

By the advances in high frequency communication systems, and particularly Internet, wide bandwidth and high-speed transistors became key devices for the circuits. Especially, optical fibres can transport data at high rates. Therefore, high-speed electronics is necessary for all kind of data processing. One limitation is the ultra high frequency modulation of the light for data transport. This requires high frequency and high voltage of operation. Second, high linearity of amplification is necessary for analog-to-digital conversion (ADCs). Indium Phosphide based Heterojunction Bipolar Transistors (InP HBTs) have the potential to provide high speed and high voltage for optoelectronic communication ICs. Moreover, since their energy band gap corresponds to the 1.3 and 1.55 µm wavelength, which are the wavelengths providing minimum optical loss in fibres, InP HBTs are the best choices for optical communication circuits. In this work, a process technology is developed for HBTs capable of 80Gbit/s. The theory and also careful analysis have shown that the main limitations for the device speed are the base-collector capacitances and base resistances. Various designs are proposed to lower RC time constant. The influence of emitter size is observed on RF performance and for optical lithography it is found out that emitters with area of 1x15 µm2 provides the best RF performance. Another important aspect is to lower any additional parasitic effects. Therefore directly contacted emitters are proposed to eliminate parasitic components caused by dummy pads and to dissipate the heat overall the emitter efficiently. Since the contact spacing between base and emitter plays an important role for base resistance, emitter contacts are patterned perpendicular to the major flat for low underetching. In addition to this, emitter mesa wet chemical etching process is optimised and 170 nm of underetching is achieved, which is sufficient to realize 1 µm width emitters. A mask set is designed offering directly contacted emitters and reliable processes. To reduce the base resistance, Pt/Ti/Pt/Au contact metal system providing 4x10?7 Ohm.cm2 contact resistance, is used on the base layer. Moreover, current density is also an important aspect for the RF performance. The well-known Kirk Effect is analysed and the collector layer is doped to improve the maximum current density. 1x1017 cm-3 of collector doping density has doubled the maximum current density in comparison to the HBTs with non-intentionally doped collector layers. For HBTs with an emitter area of 1x15 µm2 on the optimised layer structure, presented maximum oscillation frequency (fmax) of 330 GHz and cut-off frequency (fT) of 170 GHz at 1.2 mA/µm2. 1 µm is the minimum width achievable by wet chemical etching. But on the other hand, for ultra high speed HBTs, submicron emitters are dispensable. Therefore, an ICP-RIE process with Cl2/N2 chemistry providing less emitter underetching is optimised. According to this, dry etching processes offering etch rate of 120 nm/min up to 1200 nm/min are optimised. For HBTs lower etch rate, vertical sidewall profile less damage to the surface are important aspects. An etch rate of 120 nm/min is sufficient for emitter mesa etching. Therefore, this process is investigated in details. It is found out that, RMS surface roughness less than 5 nm, ± 5 % uniformity over 2” wafer and ± 5 % run-to-run stability can be achieved at this low etch rates. Since the dry etching with this chemistry is not selective for InP and InGaAs, a hybrid etching process is sufficient to complete the emitter mesa etching. With this hybrid etching, the selectivity problem is solved with an emitter underetching of 85 nm. HBTs with an emitter area of 0.5x7.5 µm2 processed with hybrid etching, has shown a maximum oscillation frequency of 370 GHz and a cut-off frequency of 165 GHz. Not only the RF performance but also the uniformity of the HBT properties is also an important aspect for circuit applications. Hbyrid etching process offers better homogeneity in terms of etching in comparison to the solely wet chemical etching. The samples etched with wet chemical etching have shown dc current gain 41 with 4 % standard deviation where the solely etched ones have presented dc current gain of 64 with 7 % standard deviation. The yield for both type of processing is more than 90 %.With the optimised layout, layer structure and processing, InP HBTs with high speed, high yield and high uniformity are now ready for 80 Gbit/s communication circuits