134 research outputs found

    Analog adaptive nonlinear filtering and spectral analysis for low-power audio applications

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, September 2006."August 2006."Includes bibliographical references.Filters are one of the basic building blocks of analog circuits. For linear operation, the power consumption is proportional to the dynamic range for a given topology. I have explored techniques to lower the power consumption below this limit by extending operation beyond the linear range. First, I built a power-efficient linear gm-C filter that demonstrates that dynamic range can be shifted to higher linear ranges using capacitive attenuation. In a standard gm-C filter, the minimum noise is limited by the discrete charge on the electrons and holes stored on the capacitor. This noise can only be reduced by collecting more charge on a larger capacitor, consuming more power. The maximum signal is determined by the linear range of the transconductor. This work showed that both the noise and the maximum signal can be amplified by including a capacitive attenuator in the feedback path of filter. In order to increase the dynamic range, I explored the non-linear operation of the filters, including jump resonance. Unlike harmonic distortion and gain compression which slowly increase with the input amplitude, jump resonance is not present in a linear system, but develops in the presence of strong nonlinearity.(cont.) It is characterized by a discontinuous jump in the frequency response near the resonant peak. I have analyzed the behavior using both describing function and state-space techniques. Then, I developed a novel graphical analysis technique. Finally, I design, built, and tested a circuit for avoiding jump resonance for audio filters. Finally, I took advantage of nonlinearities in a filtering system to build a micropower companding speech processor. This system implements the companding speech processing algorithm to improve speech comprehension in moderate noise environments. The sixteen channel system increases the spectral contrast of speech signals by performing an adjustable two-tone suppression function, replacing the function of a normally function cochlea for hearing aid or cochlear implant users. The system runs on less than 60uW of power, a consumption so low it could run for 6 months on a standard hearing aid battery.by Christopher D. Salthouse.Ph.D

    Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

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    In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

    Low-Power Low-Noise CMOS Analog and Mixed-Signal Design towards Epileptic Seizure Detection

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    About 50 million people worldwide suffer from epilepsy and one third of them have seizures that are refractory to medication. In the past few decades, deep brain stimulation (DBS) has been explored by researchers and physicians as a promising way to control and treat epileptic seizures. To make the DBS therapy more efficient and effective, the feedback loop for titrating therapy is required. It means the implantable DBS devices should be smart enough to sense the brain signals and then adjust the stimulation parameters adaptively. This research proposes a signal-sensing channel configurable to various neural applications, which is a vital part for a future closed-loop epileptic seizure stimulation system. This doctoral study has two main contributions, 1) a micropower low-noise neural front-end circuit, and 2) a low-power configurable neural recording system for both neural action-potential (AP) and fast-ripple (FR) signals. The neural front end consists of a preamplifier followed by a bandpass filter (BPF). This design focuses on improving the noise-power efficiency of the preamplifier and the power/pole merit of the BPF at ultra-low power consumption. In measurement, the preamplifier exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of bandwidth (BW), 5.86-μVrms input-referred noise in AP mode, while showing 39.4-dB DC gain, 0.36 Hz to 1.3 kHz of BW, 3.07-μVrms noise in FR mode. The preamplifier achieves noise efficiency factor (NEF) of 2.93 and 3.09 for AP and FR modes, respectively. The preamplifier power consumption is 2.4 μW from 2.8 V for both modes. The 6th-order follow-the-leader feedback elliptic BPF passes FR signals and provides -110 dB/decade attenuation to out-of-band interferers. It consumes 2.1 μW from 2.8 V (or 0.35 μW/pole) and is one of the most power-efficient high-order active filters reported to date. The complete front-end circuit achieves a mid-band gain of 38.5 dB, a BW from 250 to 486 Hz, and a total input-referred noise of 2.48 μVrms while consuming 4.5 μW from the 2.8 V power supply. The front-end NEF achieved is 7.6. The power efficiency of the complete front-end is 0.75 μW/pole. The chip is implemented in a standard 0.6-μm CMOS process with a die area of 0.45 mm^2. The neural recording system incorporates the front-end circuit and a sigma-delta analog-to-digital converter (ADC). The ADC has scalable BW and power consumption for digitizing both AP and FR signals captured by the front end. Various design techniques are applied to the improvement of power and area efficiency for the ADC. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588-μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6-μm CMOS process. The die size is 11.25 mm^2. The proposed circuits can be extended to a multi-channel system, with the ADC shared by all channels, as the sensing part of a future closed-loop DBS system for the treatment of intractable epilepsy

    Ultra low power wearable sleep diagnostic systems

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    Sleep disorders are studied using sleep study systems called Polysomnography that records several biophysical parameters during sleep. However, these are bulky and are typically located in a medical facility where patient monitoring is costly and quite inefficient. Home-based portable systems solve these problems to an extent but they record only a minimal number of channels due to limited battery life. To surmount this, wearable sleep system are desired which need to be unobtrusive and have long battery life. In this thesis, a novel sleep system architecture is presented that enables the design of an ultra low power sleep diagnostic system. This architecture is capable of extending the recording time to 120 hours in a wearable system which is an order of magnitude improvement over commercial wearable systems that record for about 12 hours. This architecture has in effect reduced the average power consumption of 5-6 mW per channel to less than 500 uW per channel. This has been achieved by eliminating sampled data architecture, reducing the wireless transmission rate and by moving the sleep scoring to the sensors. Further, ultra low power instrumentation amplifiers have been designed to operate in weak inversion region to support this architecture. A 40 dB chopper-stabilised low power instrumentation amplifiers to process EEG were designed and tested to operate from 1.0 V consuming just 3.1 uW for peak mode operation with DC servo loop. A 50 dB non-EEG amplifier continuous-time bandpass amplifier with a consumption of 400 nW was also fabricated and tested. Both the amplifiers achieved a high CMRR and impedance that are critical for wearable systems. Combining these amplifiers with the novel architecture enables the design of an ultra low power sleep recording system. This reduces the size of the battery required and hence enables a truly wearable system.Open Acces

    Neurocomputing systems for auditory processing

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    This thesis studies neural computation models and neuromorphic implementations of the auditory pathway with applications to cochlear implants and artificial auditory sensory and processing systems. Very low power analogue computation is addressed through the design of micropower analogue building blocks and an auditory preprocessing module targeted at cochlear implants. The analogue building blocks have been fabricated and tested in a standard Complementary Metal Oxide Silicon (CMOS) process. The auditory pre-processing module design is based on the cochlea signal processing mechanisms and low power microelectronic design methodologies. Compared to existing preprocessing techniques used in cochlear implants, the proposed design has a wider dynamic range and lower power consumption. Furthermore, it provides the phase coding as well as the place coding information that are necessary for enhanced functionality in future cochlear implants. The thesis presents neural computation based approaches to a number of signal-processing problems encountered in cochlear implants. Techniques that can improve the performance of existing devices are also presented. Neural network based models for loudness mapping and pattern recognition based channel selection strategies are described. Compared with state—of—the—art commercial cochlear implants, the thesis results show that the proposed channel selection model produces superior speech sound qualities; and the proposed loudness mapping model consumes substantially smaller amounts of memory. Aside from the applications in cochlear implants, this thesis describes a biologically plausible computational model of the auditory pathways to the superior colliculus based on current neurophysiological findings. The model encapsulates interaural time difference, interaural spectral difference, monaural pathway and auditory space map tuning in the inferior colliculus. A biologically plausible Hebbian-like learning rule is proposed for auditory space neural map tuning, and a reinforcement learning method is used for map alignment with other sensory space maps through activity independent cues. The validity of the proposed auditory pathway model has been verified by simulation using synthetic data. Further, a complete biologically inspired auditory simulation system is implemented in software. The system incorporates models of the external ear, the cochlea, as well as the proposed auditory pathway model. The proposed implementation can mimic the biological auditory sensory system to generate an auditory space map from 3—D sounds. A large amount of real 3-D sound signals including broadband White noise, click noise and speech are used in the simulation experiments. The efiect of the auditory space map developmental plasticity is examined by simulating early auditory space map formation and auditory space map alignment with a distorted visual sensory map. Detailed simulation methods, procedures and results are presented

    Very large time constant Gm-C Filters

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    In this study a set of tools for the design of fully integrated transconductor-capacitor (Gm-C) filters, with very large time constants and current consumption under one micro-Ampere are presented. The selected application is a 2nd order bandpass-filter-amplifier, with a gain of 400 from 0.5 to 7Hz, carrying out the signal conditioning of a piezoelectric accelerometer which is part of an implantable cardiac pacemaker. The main challenge is to achieve very large time constants, without using any discrete external component. The chosen circuit technique to fulfill the requirement is series-parallel current division applied to standard symmetrical transconductors (OTAs). These circuits have demonstrated to be an excellent solution regarding their occupied area, power consumption, noise, linearity, and particularly offset. OTAs as low as 33pS -equivalent to a 30G resistor-, with up to 1V linear range, and input referred offset of a few mV, were designed, fabricated in a standard 0.8 micron CMOS technology, and tested. The application requires the series-parallel association of a large number of transistors, and the use of bias currents as low as a few pico-Amperes, which is not very common in analog integrated circuits. In this case the designer should employ maximum care in the selection of the transistor models to be used. A central aspect of this thesis was also to evaluate and develop noise and offset estimation models which was not obvious in the very beginning of the research. In the first two chapters an introduction to the target application is presented, and several MOS transistor characteristics in terms of the inversion coefficient -using the ACM transistor model- are evaluated. In chapter 3 it is discussed whether the usual flicker and thermal noise models are consistent regarding series-parallel association, and adequately represent the expected noise behavior under different bias conditions. A consistent, physics-based, one-equation-all-regions model for flicker noise in the MOS transistor is then presented. Several noise measurements are included demonstrating that the new model accurately fits widely different bias situations. A new model for mismatch offset in MOS transistors is presented, as a corollary of the flicker noise analysis. Finally, the correlation between flicker noise and mismatch offset, that can be seen as a DC noise, is shown. In chapter 4, the design of OTAs with an extended linear range, and very low transconductance, using series-parallel current division is presented. Precise tools are introduced for the estimation of noise and mismatch offset in series-parallel current mirrors, that are shown to help in the reduction of inaccuracies in the copy of currents with a large copy factor. The design and measurement of several OTA examples are presented. In chapter 5, the developed tools, and the OTAs shown, are employed in the design of the above mentioned filter for the piezoelectric accelerometer. A general methodology for the design of Gm-C filters with similar characteristics is established. The filter was fabricated and tested, successfully operating with a total power consumption of 233nA, up to a 2V power supply, with an input noise and mismatch offset of 2-4 Vrms, and 18 V respectively. To summarize the main results obtained were: The development of a new flicker noise model, the study of the effect of mismatch regarding series-parallel association, a new design methodology for OTAs and Gm-C filters. It is our hope that this constitutes a helpful set of tools for the circuit designer.En esta tesis se presenta un conjunto de herramientas para el diseño de circuitos integrados que implementan filtros transconductor-capacitor (Gm-C), de muy altas constantes de tiempo, con bajo ruido, y consumo de corriente por debajo del micro-Ampere. Como ejemplo de aplicación se toma un amplificador-pasabanda 2º orden, de ganancia 400 en la banda de 0.5 a 7Hz, que realiza el acondicionamiento de señal de un acelerómetro piezoeléctrico a ser empleado en un marcapasos implantable. El principal desafío es realizar en dicho filtro de tiempo continuo, muy altas constantes de tiempo sin usar componentes externos. La técnica elegida para alcanzar tal objetivo es la división serie-paralelo de corriente en transconductores (OTAs) simétricos estándar. Estos circuitos demostraron ser una excelente solución en cuanto al área ocupada, su consumo, ruido, linealidad, y en particular offset. Se diseñaron, fabricaron, y midieron, OTAs hasta 33pS -equivalente a una resistencia de 30G -, con hasta 1V de rango de lineal, y offset a la entrada de algunos mV, utilizando una tecnología CMOS de 0.8 micras de largo mínimo de canal. La aplicación requiere la asociación serie-paralelo de un gran número de transistores, y polarización con corrientes de hasta pico-Amperes, lo que constituye una situación poco frecuente en circuitos integrados analógicos. En este marco el diseñador debe elegir los modelos de transistor con sumo cuidado. Un aspecto central de esta tesis es también, el estudio y presentación de modelos adecuados de ruido y offset, que no resultan obvios al principio. En los primeros dos capítulos se realiza una introducción y se revisa, utilizando el modelo ACM, diferentes características del transistor MOS en función del nivel de inversión. En el capítulo 3 revisa la pertinencia y consistencia frente a la asociación serie-paralelo, de los modelos usuales de ruido de flicker o 1/f, y térmico. Luego se presenta, incluyendo medidas, un nuevo modelo físico, consistente, simple, y válido en todas las regiones de operación del transistor MOS, para el ruido de flicker. Como corolario a este estudio se presenta un nuevo modelo para estimar el desapareo entre transistores, en función no solo de la geometría, pero también de la polarización. Se demuestra la correlación, debido a su origen físico análogo, entre el ruido de flicker y el offset por desapareo que puede ser visto como un ruido en DC. En el capítulo 4 se presenta el diseño de OTAs con rango de linealidad extendido, y muy baja transconductancia, utilizando división serie-paralelo de corriente. Se presentan herramientas precisas para la estimación de offset y ruido y se demuestra la utilidad de la técnica para reducir el offset en espejos de corriente. Se presenta el diseño y medida de diversos OTAs. En el capítulo 5, las herramientas desarrolladas, y los OTAs presentados, son empleados en el diseño del filtro descripto para un acelerómetro piezoeléctrico. Se establece una metodología general para el diseño de filtros Gm-C con características similares. El filtro se fabricó y midió, operando en forma satisfactoria, con un consumo total de 230nA y hasta los 2V de tensión de alimentación, con ruido y offset a la entrada de tan solo 2-4 Vrms, y 18 V respectivamente. El desarrollo de un nuevo modelo de ruido 1/f para el transistor MOS, el estudio de la influencia del offset frente a la asociación serie-paralelo y su aplicación en OTAs, la metodología de diseño empleada, la demostración del uso de técnicas novedosas en una aplicación como la elegida que tiene relevancia tecnológica e interés académico; esperamos que todo ello constituya una contribución valiosa para la comunidad científica en microelectrónica y un conjunto de herramientas de utilidad para el diseño de circuitos

    An electronic neuromorphic system for real-time detection of High Frequency Oscillations (HFOs) in intracranial EEG

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    In this work, we present a neuromorphic system that combines for the first time a neural recording headstage with a signal-to-spike conversion circuit and a multi-core spiking neural network (SNN) architecture on the same die for recording, processing, and detecting High Frequency Oscillations (HFO), which are biomarkers for the epileptogenic zone. The device was fabricated using a standard 0.18μ\mum CMOS technology node and has a total area of 99mm2^{2}. We demonstrate its application to HFO detection in the iEEG recorded from 9 patients with temporal lobe epilepsy who subsequently underwent epilepsy surgery. The total average power consumption of the chip during the detection task was 614.3μ\muW. We show how the neuromorphic system can reliably detect HFOs: the system predicts postsurgical seizure outcome with state-of-the-art accuracy, specificity and sensitivity (78%, 100%, and 33% respectively). This is the first feasibility study towards identifying relevant features in intracranial human data in real-time, on-chip, using event-based processors and spiking neural networks. By providing "neuromorphic intelligence" to neural recording circuits the approach proposed will pave the way for the development of systems that can detect HFO areas directly in the operation room and improve the seizure outcome of epilepsy surgery.Comment: 16 pages. A short video describing the rationale underlying the study can be viewed on https://youtu.be/NuAA91fdma

    Modeling and design of an active silicon cochlea

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references.Silicon cochleas are inspired by the biological cochlea and perform efficient spectrum analysis: They realize a bank of constant-Q Nth-order filters with O(N) efficiency rather than O(N²) efficiency due to their use of an exponentially tapered filter cascade. They are useful in speech-recognition front ends, cochlear implants, and hearing aids, especially as architectures for improving spectral analysis in noisy environments and for performing low-power spectrum analysis. In this thesis I describe four contributions towards improving the state-of-the-art in silicon-cochlea design, two of which involve theoretical modeling, and two of which involve integrated-circuit design. On the theoretical side, I first show that a simple rational approximation to distributed partition impedances in the biological cochlea captures its essential features and enables an efficient artificial implementation achieving maximum gain in a minimum number of stages while still maintaining stability. In particular, I show that the terminating impedance of the cochlea is crucial for its stability and discuss various analytic methods for termination. Second, I derive a novel composite artificial cochlear architecture composed of a cascade of all-pass second-order filters from a first-principles analysis of the biological cochlear transmission line. The novel all-pass architecture reduces phase lag and group delay in the silicon cochlea, a problem in prior designs, sharpens its high-frequency rolloff slopes, increases its frequency selectivity, and improves its nonlinear compression characteristics. On the circuit side, I first present a novel current-mode log-domain topology that simultaneously increases signal-to-noise ratio (SNR) and dynamic range while lowering power consumption in resonant filters with high quality factor Q.(cont.) The novel topology is validated in a second-order low-pass resonant filter, which is employed in the silicon cochlea, demonstrating a reduction in power consumption and increase in SNR by a factor of Q. When bias currents in the filter are adjusted as the signal level varies, this technique enables an improvement in maximum SNR by a factor of Q and an increase in maximum non-distorted signal power and dynamic range by a factor of Q⁴. Measurements from a chip in a 0.18-[mu]m 1.1-V CMOS technology achieve a quiescent power consumption of 580-nW at a 15-kHz center frequency with a maximum SNR of 41.3dB and dynamic range of 76dB for a Q=4. Finally, I describe a current-mode -stage 0.18-[mu]m silicon cochlea that achieves 79dB of dynamic range with 41-[mu]W power consumption on a 1-V power supply over a usable 3.5kHz-14kHz frequency range. These numbers represent an 18dB improvement in dynamic range and a 12.5x reduction in power consumption over prior state-of-the-art silicon cochleas.by Serhii M. Zhak.Ph.D
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