Implémentation, ajustement laser et modélisation des convertisseurs numériques à analogique R2R

La conversion numérique à analogique -- Principales caractéristiques des CNA -- Algorithmes et architectures de conversion -- Techniques de linéarisation -- Le CNA R2R inversé -- Un CNA 14 bits ajusté au laser et fabriqué dans une technologie CMOS standard -- Puce -- Montage de test -- Notes et résultats de tests -- Une compensation améliorée pour les interrupteurs des CNA R2R inversés -- Modélisation des CNA R2R

High-Accuracy Digital to Analog Converter Dedicated to Sine-Waveform Generator for Avionic Applications

RÉSUMÉ De nos jours, malgré les avancées remarquables de la microélectronique, les systèmes avioniques emploient essentiellement des technologies vieillissantes afin de répondre aux normes de sécurité exigeantes des systèmes avioniques. La nouvelle génération d'avionique modulaire intégrée (AMI) des More Electric Aircrafts (MEA), nécessite des architectures de réseaux stables et fiables, employant des modules électroniques intégrables modernes qui restent à être conçus et développés. Suivant cette tendance, une interface générique intelligente pour capteurs (Smart Sensor Interface - SSI), dédiée aux capteurs de position avionique est proposée dans ce mémoire. Le circuit intégré SSI fera partie d'un réseau de capteurs AFDX amélioré et est composé de signaux d'excitation et de modules d'acquisition de données. Les efforts de conception sont concentrés sur l'unité de génération de signaux d'excitation (Excitation Signal Generation - ESG) de la SSI. En tant que lien entre le réseau AFDX et les capteurs de déplacement, l'unité ESG doit générer des signaux sinusoïdaux précis, d'une fréquence allant de 1.5 kHz à 10 kHz. En respectant la programmation de l'interface, nous démontrerons qu'une architecture de générateur de signaux basée sur la mémoire est la seule option qui réponde aux objectifs du design. Le design d'un convertisseur numérique-analogique (CNA) basé sur le principe du sur-échantillonnage et faisant partie du chemin ESG est également présenté dans ce travail. Ce CNA est le noyau d'un générateur de signaux sinusoïdaux versatile conçu pour le système SSI proposé. Un taux d'échantillonnage élevé est utilisé dans ce CNA, de façon à obtenir un rapport signal sur bruit (Signal to Noise Ratio - SNR) élevé. Une analyse de l'impact d'une implémentation carrée et non-carrée de la matrice de sources de courant (Current Source Array - CSA) sur la performance de la séquence de commutation est présentée. Il sera démontré que la considération de tels impacts conduit à la conception de CNA plus précis. Une séquence de commutation optimale pour la taille du CSA conçu, sera introduite. Afin de réduire la taille des plots d'entrées et de sorties de la puce, un convertisseur de données série à parallèle haute-vitesse est inclu dans le CNA. Ainsi, les données d'entrée peuvent être envoyées de façon sérielle à un registre à décalage et appliquées de façon interne au noyau du CNA.----------ABSTRACT Today, despite the astonishing advances in the field of Microelectronics, avionics systems are mostly employing older technologies to guarantee the level of reliability required by stringent safety standards of avionic systems. Toward the new generation of Integrated Modular Avionics (IMA) in More Electric Aircrafts (MEA), reliable and stable network architecture which employs modern integrated electronic modules must be designed and developed. In this trend, a generic Smart Sensor Interface (SSI) for avionics displacement sensors will be proposed in this Master thesis. The integrated SSI circuit will be part of an improved AFDX sensor network and consists of signal excitation and data acquisition paths. The design efforts of this Master thesis will focus on the Excitation Signal Generation (ESG) unit of the SSI. As a link between AFDX network and displacement sensors, the ESG unit should generate pure and accurate sine-waveform with variable frequency between 1.5 kHz and 10 kHz. Respecting the programmability of the interface, it will be shown that a memory-based signal generator architecture is the only choice which supports the design objectives. As part of the ESG path, the detailed design of a 10-bit interpolating digital to analog converter (DAC) will also be presented in this work. The DAC is the core of a versatile sine-waveform generator unit designed for avionics SSI. High-speed sample rate will be used in this segmented current steering DAC in order to achieve a high Signal to Noise Ratio (SNR). In the module level design of the DAC, the impact of square and non-square implementation of the current source array (CSA) on the performance of the switching sequence is introduced. It will be shown that considering such impacts will lead to the design of more accurate DACs. An optimum switching sequence for the designed CSA size will be designed and introduced. In order to reduce the I/O pads of the chip, high-speed serial to parallel converter will be included in the DAC. Thus the input data can be serially sent to the input shift register and internally applied to the DAC core. The DAC was fabricated on 1.2 × 1.2 mm2 chip fabricated using IBM 0.13µm CMOS technology, operating with a supply voltage of 1.2 V. Sourcing a sine wave current with a peak of 1023 µA, the proposed DAC is able to achieve a SNR better than 84 dB in the Nyquist bandwidth of DC to 20 kHz

A programmable stimulator for functional electrical stimulation

Master'sMASTER OF ENGINEERIN

Development of Robust Analog and Mixed-Signal Circuits in the Presence of Process- Voltage-Temperature Variations

Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts. The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13µm CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18µm CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2. An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18µm CMOS technology. Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies

Noise-Shaping SAR ADCs.

This work investigates hybrid analog-to-digital converters (ADCs) that combine the phenomenal energy efficiency of successive-approximation (SAR) ADCs with the resolution enhancement strategies used by noise-shaping converters. Because charge-redistribution SAR ADCs contain few active components and rely on highly digital controllers, SAR ADCs demonstrate the best energy efficiencies of all low bandwidth, moderate resolution converters (~10 bits). SAR ADCs achieve remarkable power efficiency at low resolution, but as the resolution of the SAR ADC increases, the specifications for input-referred comparator noise become more stringent and total DAC capacitance becomes too large, which degrades both power efficiency and bandwidth. For these reasons, lower resolution, lower bandwidth applications tend to favor traditional SAR ADC architectures, while higher bandwidth, higher resolution applications tend to favor pipeline-SARs. Although the use of amplifiers in pipeline-assisted SARs relaxes the comparator noise requirements and improves bandwidth, amplifier design becomes more of a challenge in highly scaled processes with reduced supply voltages. In this work, we explore the use of feedback and noise-shaping to enhance the resolution of SAR ADCs. Unlike pipeline-SARs, which require high-gain, linear amplifiers, noise-shaping SARs can be constructed using passive FIR filter structures. Furthermore, the use of feedback and noise-shaping reduces the impact of thermal kT/C noise and comparator noise. This work details and explores a new class of noise-shaping SARs.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/113647/1/fredenbu_1.pd

Digital Signal Processing for Optical Communications and Coherent LiDAR

Internet data traffic within data centre, access and metro networks is experiencing unprecedented growth driven by many data-intensive applications. Significant efforts have been devoted to the design and implementation of low-complexity digital signal processing (DSP) algorithms that are suitable for these short-reach optical links. In this thesis, a novel low-complexity frequency-domain (FD) multiple-input multiple-output (MIMO) equaliser with momentum-based gradient descent algorithm is proposed, capable of mitigating both static and dynamic impairments arising from the optical fibre. The proposed frequency-domain equaliser (FDE) also improves the robustness of the adaptive equaliser against feedback latencies which is the main disadvantage of FD adaptive equalisers under rapid channel variations. The development and maturity of optical fibre communication techniques over the past few decades have also been beneficial to many other fields, especially coherent light detection and ranging (LiDAR) techniques. Many applications of coherent LiDAR are also cost-sensitive, e.g., autonomous vehicles (AVs). Therefore, in this thesis, a low-cost and low-complexity single-photodiode-based coherent LiDAR system is investigated. The receiver sensitivity performance of this receiver architecture is assessed through both simulations and experiments, using two ranging waveforms known as double-sideband (DSB) amplitude-modulated chirp signal and single-sideband (SSB) frequency-modulated continuous-wave (FMCW) signals. Besides, the impact of laser phase noise on the ranging precision when operating within and beyond the laser coherence length is studied. Achievable ranging precision beyond the laser coherence length is quantified

Enhancing the sensitivity of future laser-interferometric gravitational wave detectors

The first direct detection of gravitational waves last year was the beginning of a new field of astronomy. While we have already learned a great deal from the signals sensed by the LIGO interferometers in their first observation run, research is already underway to improve upon the sensitivity of the state of the art detectors. Novel mirror designs, new interferometer topologies and larger, more advanced detectors are all being considered as future improvements, and these topics form the focus of this thesis. A reduction in the thermal noise arising from the mirrors within gravitational wave detectors will enhance sensitivity near their most sensitive frequencies, and this can potentially be achieved through the use of waveguide mirrors employing gratings. It has been shown that the thermal noise is reduced in waveguide mirrors compared to standard dielectric mirrors whilst retaining the required reflectivity, but an open question regarding their suitability remains due to the potential for increased technical noise coupling created by the substructure. We place an upper limit on this coupling with a suspended cavity experiment, showing that this approach to the design of grating mirrors has promise. While the use of higher classical laser input initially increases interferometer sensitivity, eventually the Michelson interferometer topology employed in existing detectors reaches the standard quantum limit preventing further enhancement. Efforts are being made to test the suitability of so-called quantum non-demolition (QND) technologies able to surpass this limit, one of which involves the use of a new interferometer topology altogether. An experiment to demonstrate a reduction in quantum radiation pressure noise in a QND-compatible Sagnac speed meter topology is underway in Glasgow, and we introduce novel techniques to control this suspended, audio-band interferometer to inform the technical design of future detectors wishing to measure beyond the standard quantum limit. In particular, the problem of controlling the interferometer at low frequencies is discussed. Due to the nature of the speed meter topology, the response of the interferometer vanishes towards zero frequency, while the interferometer's noise does not. This creates a control problem at low frequencies where test mass perturbations arising from, for example, seismic and electronic noise, can lead to loss of interferometer sensitivity over the course of minutes to hours. We present a solution involving the blending of signals from different readout ports of the interferometer, facilitating measurements with almost arbitrary integration times. The longer, larger Einstein Telescope facility planned as part of the next generation of detectors will push the Michelson interferometer topology to the limit. The low frequency interferometer will utilise optomechanical interactions to enhance its sensitivity at low frequencies, and the control problems associated with this technique have not been investigated in detail. Following the approach taken in the current generation of detectors we show that the interferometer can be controlled without adversely affecting its sensitivity to gravitational waves, paving the way for a future technical design

Efficient DSP and Circuit Architectures for Massive MIMO: State-of-the-Art and Future Directions

Massive MIMO is a compelling wireless access concept that relies on the use of an excess number of base-station antennas, relative to the number of active terminals. This technology is a main component of 5G New Radio (NR) and addresses all important requirements of future wireless standards: a great capacity increase, the support of many simultaneous users, and improvement in energy efficiency. Massive MIMO requires the simultaneous processing of signals from many antenna chains, and computational operations on large matrices. The complexity of the digital processing has been viewed as a fundamental obstacle to the feasibility of Massive MIMO in the past. Recent advances on system-algorithm-hardware co-design have led to extremely energy-efficient implementations. These exploit opportunities in deeply-scaled silicon technologies and perform partly distributed processing to cope with the bottlenecks encountered in the interconnection of many signals. For example, prototype ASIC implementations have demonstrated zero-forcing precoding in real time at a 55 mW power consumption (20 MHz bandwidth, 128 antennas, multiplexing of 8 terminals). Coarse and even error-prone digital processing in the antenna paths permits a reduction of consumption with a factor of 2 to 5. This article summarizes the fundamental technical contributions to efficient digital signal processing for Massive MIMO. The opportunities and constraints on operating on low-complexity RF and analog hardware chains are clarified. It illustrates how terminals can benefit from improved energy efficiency. The status of technology and real-life prototypes discussed. Open challenges and directions for future research are suggested.Comment: submitted to IEEE transactions on signal processin