Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer¬based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase¬locked loop (PLL)¬based synthesizers. Harmonic cancela¬tion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ¬120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD¬QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im¬plemented with three stages in 0.18 µm CMOS technology, the ILFD draws 3¬mA current from a 1.8¬V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range

Design of injection locked frequency divider in 65nm CMOS technology for mmW applications

In this paper, an Injection Locking Frequency Divider (ILFD) in 65 nm RF CMOS Technology for applications in millimeter-wave (mm-W) band is presented. The proposed circuit achieves 12.69% of locking range without any tuning mechanism and it can cover the entire mm-W band in presence of Process, Voltage and Temperature (PVT) variations by changing the Injection Locking Oscillator (ILO) voltage control. A design methodology flow is proposed for ILFD design and an overview regarding CMOS capabilities and opportunities for mm-W transceiver implementation is also exposed.Postprint (published version

Receiver Front-Ends in CMOS with Ultra-Low Power Consumption

Historically, research on radio communication has focused on improving range and data rate. In the last decade, however, there has been an increasing demand for low power and low cost radios that can provide connectivity with small devices around us. They should be able to offer basic connectivity with a power consumption low enough to function extended periods of time on a single battery charge, or even energy scavenged from the surroundings. This work is focused on the design of ultra-low power receiver front-ends intended for a receiver operating in the 2.4GHz ISM band, having an active power consumption of 1mW and chip area of 1mm². Low power consumption and small size make it hard to achieve good sensitivity and tolerance to interference. This thesis starts with an introduction to the overall receiver specifications, low power radio and radio standards, front-end and LO generation architectures and building blocks, followed by the four included papers. Paper I demonstrates an inductorless front-end operating at 915MHz, including a frequency divider for quadrature LO generation. An LO generator operating at 2.4GHz is shown in Paper II, enabling a front-end operating above 2GHz. Papers III and IV contain circuits with combined front-end and LO generator operating at or above the full 2.45GHz target frequency. They use VCO and frequency divider topologies that offer efficient operation and low quadrature error. An efficient passive-mixer design with improved suppression of interference, enables an LNA-less design in Paper IV capable of operating without a SAW-filter

Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer¬based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase¬locked loop (PLL)¬based synthesizers. Harmonic cancela¬tion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ¬120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD¬QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im¬plemented with three stages in 0.18 µm CMOS technology, the ILFD draws 3¬mA current from a 1.8¬V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range

A GSM-GPRS/UMTS FDD-TDD/WLAN 802.11a-b-g multi-standard carrier generation system

A compact carrier generation system enabling proper interoperability among quad-band GSM, WCDMA (FDD and TDD), and WLAN (802.11a/b/g) standards is developed. The implementation is achieved in 0.25-mum BiCMOS-SiGe process. The measured tuning range is higher that 1 GHz (3.05 to 4.1 GHz) exceeding the specifications by 25%. The voltage-controlled oscillator (VCO) exhibits a phase noise of -118 and -125 dBc/Hz measured, respectively, at 400 kHz and 1 MHz offsets while drawing 2.5 mA from 2.5 V supply. The measured phase noise at 400 kHz offset of the PCS/DCS output local-oscillator (LO) signal and the GSM output LO signal is, respectively, -124 dBc/Hz and -130 dBc/H

Novel RF CMOS Integrated Circuits and Systems for Broadband Dielectric Spectroscopy

Broadband dielectric spectroscopy has proven to be a valuable technique for characterization of chemicals and biomaterials. It has the great potential to become an indispensable and cost-effective tool in point-of-care medical applications due to its label-free and non-invasive operation. However, most of the existing dielectric spectroscopy instruments require bulky, heavy and expensive measurement set-up, restricting their use to only special applications in industry and laboratories. Therefore, integrated dielectric spectroscopy on silicon capable of direct detection of chemicals/biomaterials' complex permittivity can yield significant cost and size reduction, system integration, portability, enormous processing, and high throughput. A CMOS wideband dielectric spectroscopy system is proposed for chemical and biological material characterization. The complex permittivity detection is performed using a configurable harmonic-rejecting receiver capable of indirectly measuring the complex admittance of sensing capacitor exposed to the material-under-test (MUT) and subject to RF signal excitation with a frequency range of 0.62-10 GHz. The sensing capacitor is embedded in a voltage divider topology with a fixed capacitor and the relative variations in the magnitude and phase of the voltages across the capacitors are used to find the real and imaginary parts of the permittivity. The sensor achieves an rms permittivity error of less than 1% over the entire operation bandwidth. Using a sub-harmonic mixing scheme, the system can perform complex permittivity measurements from 0.62 to 10 GHz while requiring an input signal source with frequency range of only from 5 to 10 GHz. Thereby, the permittivity measurement system can be easily made self-sustained by implementing a 5-10 GHz frequency synthesizer on the same chip. One of the key building blocks in such a frequency synthesizer is the voltage-controlled oscillator (VCO) which has to cover an octave of frequency range. A novel low-phase-noise wide-tuning range VCO is presented using a triple-band LC resonator. The implemented VCO in 0.18μm CMOS technology achieves a continuous tuning range of 86.7% from 5.12 GHz to 12.95 GHz while drawing 5 to 10 mA current from 1-V supply. The measured phase noise at 1 MHz offset from carrier frequencies of 5.9, 9.12 and 12.25 GHz is -122.9, -117.1 and -110.5 dBc/Hz, respectively. Also, a dual-band quadrature voltage-controlled oscillator (QVCO) is presented using a transformer-based high-order LC-ring resonator which inherently provides quadrature signals without requiring noisy coupling transistors as in traditional approaches. The proposed resonator shows two possible oscillation frequencies which are exploited to realize a wide-tuning range QVCO employing a mode-switching transistor network. Due to the use of transformers, the oscillator has minimal area penalty compared to the conventional designs. The implemented prototype in a 65-nm CMOS process achieves a continuous tuning range of 77.8% from 2.75 GHz to 6.25 GHz while consuming 9.7 to 15.6 mA current from 0.6-V supply. The measured phase noise figure-of-merit (FoM) at 1 MHz offset ranges from 184 dB to 188.2 dB throughout the entire tuning range. The QVCO also exhibits good quadrature accuracy with 1.5º maximum phase error and occupies a relatively small silicon area of 0.35 mm^2

Circuit Design Techniques For Wideband Phased Arrays

University of Minnesota Ph.D. dissertation.June 2015. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xii, 143 pages.This dissertation focuses on beam steering in wideband phased arrays and phase noise modeling in injection locked oscillators. Two different solutions, one in frequency and one in time, have been proposed to minimize beam squinting in phased arrays. Additionally, a differential current reuse frequency doubler for area and power savings has been proposed. Silicon measurement results are provided for the frequency domain solution (IBM 65nm RF CMOS), injection locked oscillator model verification (IBM 130nm RF-CMOS) and frequency doubler (IBM 65nm RF CMOS), while post extraction simulation results are provided for the time domain phased array solution (the chip is currently under fabrication, TSMC 65nm RF CMOS). In the frequency domain solution, a 4-point passive analog FFT based frequency tunable filter is used to channelize an incoming wideband signal into multiple narrowband signals, which are then processed through independent phase shifters. A two channel prototype has been developed at 8GHz RF frequency. Three discrete phase shifts (0 & +/- 90 degrees) are implemented through differential I-Q swapping with appropriate polarity. A minimum null-depth of 19dB while a maximum null-depth of 27dB is measured. In the time domain solution, a discrete time approach is undertaken with signals getting sampled in order of their arrival times. A two-channel prototype for a 2GHz instantaneous RF bandwidth (7GHz-9GHz) has been designed. A QVCO generates quadrature LO signals at 8GHz which are phase shifted through a 5-bit (2 extra bits from differential I-Q swapping with appropriate polarity) cartesian combiner. Baseband sampling clocks are generated from phase shifted LOs through a CMOS divide by 4 with independent resets. The design achieves an average time delay of 4.53ps with 31.5mW of power consumption (per channel, buffers excluded). An injection locked oscillator has been analyzed in s-domain using Paciorek's time domain transient equations. The simplified analysis leads to a phase noise model identical to that of a type-I PLL. The model is equally applicable to injection locked dividers and multipliers and has been extended to cover all injection locking scenarios. The model has been verified against a discrete 57MHz Colpitt's ILO, a 6.5GHz ILFD and a 24GHz ILFM with excellent matching between the model and measurements. Additionally, a differential current reuse frequency doubler, for frequency outputs between 7GHz to 14GHz, design has been developed to reduce passive area and dc power dissipation. A 3-bit capacitive tuning along with a tail current source is used to better conversion efficiency. The doubler shows FOM$_{T}$ values between 191dBc/Hz to 209dBc/Hz when driven by a 0.7GHz to 5.8GHz wide tuning VCO with a phase noise that ranges from -114dBc/Hz to -112dBc/Hz over the same bandwidth

Analysis and Design of a 1.8-GHz CMOS LC Quadrature VCO

This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs. A simplified theoretical analysis for the oscillation frequency and phase noise displayed by the QVCO in the 1/f/sup 3/ region is developed, and good agreement is found between theory and simulation results. A prototype for the QVCO was implemented in a 0.35-/spl mu/m CMOS process with three standard metal layers. The QVCO could be tuned between 1.64 and 1.97 GHz, and showed a phase noise of -140 dBc/Hz or less across the tuning range at a 3-MHz offset frequency from the carrier, for a current consumption of 25 mA from a 2-V power supply. The equivalent phase error between I and Q signals was at most 0.25/spl deg/

Microwave CMOS VCOs and Front-Ends - using integrated passives on-chip and on-carrier

The increasing demand for high data rates in wireless communication systems is increasing the requirements on the transceiver front-ends, as they are pushed to utilize more and wider bands at higher frequencies. The work in this thesis is focused on receiver front-ends composed of Low Noise Amplifiers (LNAs), Mixers, and Voltage Controlled Oscillators (VCOs) operating at microwave frequencies. Traditionally, microwave electronics has used exclusive and more expensive semiconductor technologies (III-V materials). However, the rapid development of consumer electronics (e.g. video game consoles) the last decade has pushed the silicon CMOS IC technology towards even smaller feature sizes. This has resulted in high speed transistors (high fT and fmax) with low noise figures. However, as the breakdown voltages have decreased, a lower supply voltage must be used, which has had a negative impact on linearity and dynamic range. Nonetheless, todays downscaled CMOS technology is a feasible alternative for many microwave and even millimeter wave applications. The low quality factor (Q) of passive components on-chip usually limits the high frequency performance. For inductors realized in a standard CMOS process the substrate coupling results in a degraded Q. The quality factor can, however, be improved by moving the passive components off-chip and integrating them on a low loss carrier. This thesis therefore features microwave front-end and VCO designs in CMOS, where some designs have been flip-chip mounted on carriers featuring high Q inductors and low loss baluns. The thesis starts with an introduction to wireless communication, receiver architectures, front-end receiver blocks, and low loss carrier technology, followed by the included papers. The six included papers show the capability of CMOS and carrier technology at microwave frequencies: Papers II, III, and VI demonstrate fully integrated CMOS circuit designs. An LC-VCO using an accumulation mode varactor is presented in Paper II, a QVCO using 4-bit switched tuning is shown in Paper III, and a quadrature receiver front-end (including QVCO) is demonstrated in paper VI. Papers I and IV demonstrate receiver front-ends using low loss baluns on carrier for the LO and RF signals. Paper IV also includes a front-end using single-ended RF input which is converted to differential form in a novel merged LNA and balun. A VCO demonstrating the benefits of a high Q inductor on carrier is presented in Paper V