55,898 research outputs found
Balance testing and balance-testable design of logic circuits
We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/43016/1/10836_2004_Article_BF00136077.pd
Emulating Digital Logic using Transputer Networks (Very High Parallelism = Simplicity = Performance)
Modern VLSI technology has changed the economic rules by which the balance between processing
power, memory and communications is decided in computing systems. This will have a profound
impact on the design rules for the controlling software. In particular, the criteria for judging efficiency
of the algorithms will be somewhat different. This paper explores some of these implications through
the development of highly parallel and highly distributable algorithms based on occam and transputer
networks. The major results reported are a new simplicity for software designs, a corresponding ability
to reason (formally and informally) about their properties, the reusability of their components and some
real performance figures which demonstrate their practicality. Some guidelines to assist in these designs
are also given. As a vehicle for discussion, an interactive simulator is developed for checking the
functional and timing characteristics of digital logic circuits of arbitrary complexity
Angle detector
An angle detector for determining a transducer's angular disposition to a capacitive pickup element is described. The transducer comprises a pendulum mounted inductive element moving past the capacitive pickup element. The capacitive pickup element divides the inductive element into two parts L sub 1 and L sub 2 which form the arms of one side of an a-c bridge. Two networks R sub 1 and R sub 2 having a plurality of binary weighted resistors and an equal number of digitally controlled switches for removing resistors from the networks form the arms of the other side of the a-c bridge. A binary counter, controlled by a phase detector, balances the bridge by adjusting the resistance of R sub 1 and R sub 2. The binary output of the counter is representative of the angle
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers
At nanometer manufacturing technology nodes, process variations significantly
affect circuit performance. To combat them, post- silicon clock tuning buffers
can be deployed to balance timing bud- gets of critical paths for each
individual chip after manufacturing. The challenge of this method is that path
delays should be mea- sured for each chip to configure the tuning buffers
properly. Current methods for this delay measurement rely on path-wise
frequency stepping. This strategy, however, requires too much time from ex-
pensive testers. In this paper, we propose an efficient delay test framework
(EffiTest) to solve the post-silicon testing problem by aligning path delays
using the already-existing tuning buffers in the circuit. In addition, we only
test representative paths and the delays of other paths are estimated by
statistical delay prediction. Exper- imental results demonstrate that the
proposed method can reduce the number of frequency stepping iterations by more
than 94% with only a slight yield loss.Comment: ACM/IEEE Design Automation Conference (DAC), June 201
A 100-MIPS GaAs asynchronous microprocessor
The authors describe how they ported an asynchronous microprocessor previously implemented in CMOS to gallium arsenide, using a technology-independent asynchronous design technique. They introduce new circuits including a sense-amplifier, a completion detection circuit, and a general circuit structure for operators specified by production rules. The authors used and tested these circuits in a variety of designs
An Energy-Efficient, Dynamic Voltage Scaling Neural Stimulator for a Proprioceptive Prosthesis
Accepted versio
Extreme ultraviolet and X-ray spectroheliograph for OSO-H
A complex scientific instrument was designed, fabricated, tested, and calibrated for launch onboard OSO-H. This instrument consisted of four spectroheliographs and an X-ray polarimeter. The instrument is designed to study solar radiation at selected wavelengths in the X-ray and the extreme ultraviolet ranges, make observations at the H-alpha wavelength, and measure the degree of polarization of X-ray emissions
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