Energy-efficient design and implementation of turbo codes for wireless sensor network

The objective of this thesis is to apply near Shannon limit Error-Correcting Codes (ECCs), particularly the turbo-like codes, to energy-constrained wireless devices, for the purpose of extending their lifetime. Conventionally, sophisticated ECCs are applied to applications, such as mobile telephone networks or satellite television networks, to facilitate long range and high throughput wireless communication. For low power applications, such as Wireless Sensor Networks (WSNs), these ECCs were considered due to their high decoder complexities. In particular, the energy efficiency of the sensor nodes in WSNs is one of the most important factors in their design. The processing energy consumption required by high complexity ECCs decoders is a significant drawback, which impacts upon the overall energy consumption of the system. However, as Integrated Circuit (IC) processing technology is scaled down, the processing energy consumed by hardware resources reduces exponentially. As a result, near Shannon limit ECCs have recently begun to be considered for use in WSNs to reduce the transmission energy consumption [1,2]. However, to ensure that the transmission energy consumption reduction granted by the employed ECC makes a positive improvement on the overall energy efficiency of the system, the processing energy consumption must still be carefully considered.The main subject of this thesis is to optimise the design of turbo codes at both an algorithmic and a hardware implementation level for WSN scenarios. The communication requirements of the target WSN applications, such as communication distance, channel throughput, network scale, transmission frequency, network topology, etc, are investigated. Those requirements are important factors for designing a channel coding system. Especially when energy resources are limited, the trade-off between the requirements placed on different parameters must be carefully considered, in order to minimise the overall energy consumption. Moreover, based on this investigation, the advantages of employing near Shannon limit ECCs in WSNs are discussed. Low complexity and energy-efficient hardware implementations of the ECC decoders are essential for the target applications

New VLSI design of a MAP/BCJR decoder.

Any communication channel suffers from different kinds of noises. By employing forward error correction (FEC) techniques, the reliability of the communication channel can be increased. One of the emerging FEC methods is turbo coding (iterative coding), which employs soft input soft output (SISO) decoding algorithms like maximum a posteriori (MAP) algorithm in its constituent decoders. In this thesis we introduce a design with lower complexity and less than 0.1dB performance loss compare to the best performance observed in Max-Log-MAP algorithm. A parallel and pipeline design of a MAP decoder suitable for ASIC (Application Specific Integrated Circuits) is used to increase the throughput of the chip. The branch metric calculation unit is studied in detail and a new design with lower complexity is proposed. The design is also flexible to communication block sizes, which makes it ideal for variable frame length communication systems. A new even-spaced quantization technique for the proposed MAP decoder is utilized. Normalization techniques are studied and a suitable technique for the Max-Log-MAP decoder is explained. The decoder chip is synthesized and implemented in a 0.18 mum six-layer metal CMOS technology. (Abstract shortened by UMI.)Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .S23. Source: Masters Abstracts International, Volume: 43-05, page: 1783. Adviser: Majid Ahmadi. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

Performance analysis of error detection and correction code for wireless sensor networks

Recent advances in wireless communications and electronics have enabled the development of low-cost, low-power, self-organizational, multifunctional wireless sensor networks. Wireless sensor networks can be applied to a wide range of application areas including heath, military and homeland security, environment, industry and commercial, and home. A typical wireless sensor network consists of one or more sink nodes and a large number of sensor nodes scattered in a sensor field. Each of these sensor nodes is capable to collect the data and relay the data back to the sink through a multi-hop architecture. The key challenge in sensor networks is to overcome the energy constraint since each sensor node has limited power. Hence, it is important to minimize the energy used to transmit packets over wireless links; The data transmitted from the sensor nodes are vulnerable to be corrupted by errors induced by noisy channels and other factors. Hence it is necessary to provide a proper error control scheme to reduce the bit error rate (BER) to a desired level without sacrificing other performance. Energy required for error control code has a direct impact on battery power consumption. Since high error rates are inevitable in the wireless environment, energy efficient error detection and correction scheme is vital in wireless sensor networks. However, in the literature, limited work has been focused on the study of energy efficient error control scheme; This thesis is focused on energy-efficient error detection and correction schemes for wireless sensor networks. (Abstract shortened by UMI.)

Iterative multiuser detection with integrated channel estimation for turbo coded DS-CDMA.

In present days the demand of high bandwidth and data rate in wireless communications is increasing rapidly to accommodate multimedia applications, including services such as wireless video and high-speed Internet access. In this thesis, we propose a receiver algorithm for mobile communications systems which apply CDMA (Code division multiple access) as multiple access technique. Multiuser Detection and turbo coding are the two most powerful techniques for enhancing the performance of future wireless services. The standardization of direct sequence CDMA (DS-CDMA) systems in the third generation of mobile communication system has raised the interest in exploiting the capabilities and capacity of this type of Technology. However the conventional DS-CDMA system has the major drawback of multiple Access Interference (MAI). The MAI is unavoidable because receivers deal with the information which is transmitted not by a single information source but by several uncoordinated and geographically separated sources. To overcome this problem MUD is a promising approach to increase capacity. (Abstract shortened by UMI.)Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2005 .C465. Source: Masters Abstracts International, Volume: 45-01, page: 0404. Thesis (M.Sc.)--University of Windsor (Canada), 2005

ON REDUCING THE DECODING COMPLEXITY OF SHINGLED MAGNETIC RECORDING SYSTEM

Shingled Magnetic Recording (SMR) has been recognised as one of the alternative technologies to achieve an areal density beyond the limit of the perpendicular recording technique, 1 Tb/in2, which has an advantage of extending the use of the conventional method media and read/write head. This work presents SMR system subject to both Inter Symbol Interference (ISI) and Inter Track Interference (ITI) and investigates different equalisation/detection techniques in order to reduce the complexity of this system. To investigate the ITI in shingled systems, one-track one-head system model has been extended into two-track one-head system model to have two interfering tracks. Consequently, six novel decoding techniques have been applied to the new system in order to find the Maximum Likelihood (ML) sequence. The decoding complexity of the six techniques has been investigated and then measured. The results show that the complexity is reduced by more than three times with 0.5 dB loss in performance. To measure this complexity practically, perpendicular recording system has been implemented in hardware. Hardware architectures are designed for that system with successful Quartus II fitter which are: Perpendicular Magnetic Recording (PMR) channel, digital filter equaliser with and without Additive White Gaussian Noise (AWGN) and ideal channel architectures. Two different hardware designs are implemented for Viterbi Algorithm (VA), however, Quartus II fitter for both of them was unsuccessful. It is found that, Simulink/Digital Signal Processing (DSP) Builder based designs are not efficient for complex algorithms and the eligible solution for such designs is writing Hardware Description Language (HDL) codes for those algorithms.The Iraqi Governmen

Physical layer network coding based on compute-and-forward

In this thesis, Compute-and-Forward is considered, where the system model consists of multiple users and a single base station. Compute-and-Forward is a type of lattice network coding which is deemed to avoid backhaul load and is therefore an important aspect of modern wireless communications networks. Initially we propose an implementation of construction D into Compute-and-Forward and investigate the implementation of multilayer lattice encoding and decoding strategies. Here we show that adopting a construction D lattice we can implement a practical lattice decoder in Compute-and-Forward. During this investigation and implementation of multilayer lattice encoding and decoding we discover an error floor due to an interaction between code layers in the multilayer decoder. We analyse and describe this interaction with mathematical expressions and give detail using lemmas and proofs. Secondly, we demonstrate the BER performance of the system model for unit valued channels, integer valued channels and complex integer valued channels. We show that using the derived expressions for interaction that the decoders on each code layer are able to indeed decode. The BER results are demonstrated for two scenarios using zero order and second order Reed-Muller codes and first and third order Reed-Muller codes. Finally, we extend our system model using construction D and existing conventional decoders to include coefficient selection algorithms. We employ an exhaustive search algorithm and analyse the throughput performance of the codes. Again, we extend this to both our models. With the throughput of the codes we see that each layer can be successfully decoded considering the interaction expressions. The purpose of the performance results is to show decodability with the extension of using differing codes

Novel Methods in the Improvement of Turbo Codes and their Decoding

The performance of turbo codes can often be improved by improving the weight spectra of such codes. Methods of producing the weight spectra of turbo codes have been investigated and many improvements were made to refine the techniques. A much faster method of weight spectrum evaluation has been developed that allows calculation of weight spectra within a few minutes on a typical desktop PC. Simulation results show that new high performance turbo codes are produced by the optimisation methods presented. The two further important areas of concern are the code itself and the decoding. Improvements of the code are accomplished through optimisation of the interleaver and choice of constituent coders. Optimisation of interleaves can also be accomplished automatically using the algorithms described in this work. The addition of a CRC as an outer code proved to offer a vast improvement on the overall code performance. This was achieved without any code rate loss as the turbo code is punctured to make way for the CRC remainder. The results show a gain of 0.4dB compared to the non-CRC (1014,676) turbo code. Another improvement to the decoding performance was achieved through a combination of MAP decoding and Ordered Reliability decoding. The simulations show a performance of just 0.2dB from the Shannon limit. The same code without ordered reliability decoding has a performance curve which is 0.6dB from the Shannon limit. In situations where the MAP decoder fails to converge ordered reliability decoding succeeds in producing a codeword much closer to the received vector, often the correct codeword. The ordered reliability decoding adds to the computational complexity but lends itself to FPGA implementation.Engineering and Physical Sciences Research Council (EPSRC