1,297 research outputs found

    Track Extrapolation and Distribution for the CDF-II Trigger System

    Get PDF
    The CDF-II experiment is a multipurpose detector designed to study a wide range of processes observed in the high energy proton-antiproton collisions produced by the Fermilab Tevatron. With event rates greater than 1MHz, the CDF-II trigger system is crucial for selecting interesting events for subsequent analysis. This document provides an overview of the Track Extrapolation System (XTRP), a component of the CDF-II trigger system. The XTRP is a fully digital system that is utilized in the track-based selection of high momentum lepton and heavy flavor signatures. The design of the XTRP system includes five different custom boards utilizing discrete and FPGA technology residing in a single VME crate. We describe the design, construction, commissioning and operation of this system.Comment: 34 pages, 9 figures, submitted to Nucl.Inst.Meth.

    Space Station Freedom data management system growth and evolution report

    Get PDF
    The Information Sciences Division at the NASA Ames Research Center has completed a 6-month study of portions of the Space Station Freedom Data Management System (DMS). This study looked at the present capabilities and future growth potential of the DMS, and the results are documented in this report. Issues have been raised that were discussed with the appropriate Johnson Space Center (JSC) management and Work Package-2 contractor organizations. Areas requiring additional study have been identified and suggestions for long-term upgrades have been proposed. This activity has allowed the Ames personnel to develop a rapport with the JSC civil service and contractor teams that does permit an independent check and balance technique for the DMS

    Intelligent redundant actuation system requirements and preliminary system design

    Get PDF
    Several redundant actuation system configurations were designed and demonstrated to satisfy the stringent operational requirements of advanced flight control systems. However, this has been accomplished largely through brute force hardware redundancy, resulting in significantly increased computational requirements on the flight control computers which perform the failure analysis and reconfiguration management. Modern technology now provides powerful, low-cost microprocessors which are effective in performing failure isolation and configuration management at the local actuator level. One such concept, called an Intelligent Redundant Actuation System (IRAS), significantly reduces the flight control computer requirements and performs the local tasks more comprehensively than previously feasible. The requirements and preliminary design of an experimental laboratory system capable of demonstrating the concept and sufficiently flexible to explore a variety of configurations are discussed

    The Level-0 Muon Trigger for the LHCb Experiment

    Get PDF
    A very compact architecture has been developed for the first level Muon Trigger of the LHCb experiment that processes 40 millions of proton-proton collisions per second. For each collision, it receives 3.2 kBytes of data and it finds straight tracks within a 1.2 microseconds latency. The trigger implementation is massively parallel, pipelined and fully synchronous with the LHC clock. It relies on 248 high density Field Programable Gate arrays and on the massive use of multigigabit serial link transceivers embedded inside FPGAs.Comment: 33 pages, 16 figures, submitted to NIM

    Hardware studies for the upgrade of the ATLAS Central Trigger Processor

    Get PDF
    The ATLAS Central Trigger Processor (CTP) is the final stage of the first level trigger system which reduces the collision rate of 40 MHz to a level-1 event rate of 75 kHz. The CTP makes the Level-1 trigger decision based on multiplicity values of various transverse-momentum thresholds as well as energy information received from the calorimeter and muon trigger sub-systems using programmable selection criteria. In order to improve the rejection rate for the first phase of the luminosity upgrade of the LHC to 3∙1034 cm-2 s-1 planned for 2015, one of the options being studied consists of adding a topological trigger processor, using Region-Of-Interest information from the calorimeter and potentially also the muon trigger. This will require an upgrade of the CTP in order to accommodate the additional trigger inputs. The current CTP system consists of a 9U VME64x crate with 11 custom designed modules where the functionality is largely implemented in FPGAs. The constraint for the upgrade study presented here was to reuse the existing hardware as much as possible. This is achieved by operating the backplane at twice the design frequency and required developing new FPGA firmware for several of the CTP modules. We present the design of the newly developed firmware for the input, monitoring and core modules of the CTP as well as results from initial tests of the upgraded system

    Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 2: Army fault tolerant architecture design and analysis

    Get PDF
    Described here is the Army Fault Tolerant Architecture (AFTA) hardware architecture and components and the operating system. The architectural and operational theory of the AFTA Fault Tolerant Data Bus is discussed. The test and maintenance strategy developed for use in fielded AFTA installations is presented. An approach to be used in reducing the probability of AFTA failure due to common mode faults is described. Analytical models for AFTA performance, reliability, availability, life cycle cost, weight, power, and volume are developed. An approach is presented for using VHSIC Hardware Description Language (VHDL) to describe and design AFTA's developmental hardware. A plan is described for verifying and validating key AFTA concepts during the Dem/Val phase. Analytical models and partial mission requirements are used to generate AFTA configurations for the TF/TA/NOE and Ground Vehicle missions

    Space Generic Open Avionics Architecture (SGOAA) reference model technical guide

    Get PDF
    This report presents a full description of the Space Generic Open Avionics Architecture (SGOAA). The SGOAA consists of a generic system architecture for the entities in spacecraft avionics, a generic processing architecture, and a six class model of interfaces in a hardware/software system. The purpose of the SGOAA is to provide an umbrella set of requirements for applying the generic architecture interface model to the design of specific avionics hardware/software systems. The SGOAA defines a generic set of system interface points to facilitate identification of critical interfaces and establishes the requirements for applying appropriate low level detailed implementation standards to those interface points. The generic core avionics system and processing architecture models provided herein are robustly tailorable to specific system applications and provide a platform upon which the interface model is to be applied

    キューブサットバスシステムのための標準化・適応性インターフェース設計

    Get PDF
    Since the 2000s, small satellite launches have increased rapidly each year and the number of players in this field is strongly linked to the popularity of the CubeSat standard around the globe. Highlights of its achievements are often the compatibility of launches via a standardized deployer (i.e. POD), shorter development times and lower costs than conventional large satellites. CubeSats are not just popular instruments for educating students in space research and engineering, but also enable us to demonstrate challenging technologies in a cheaper and quicker way and carry out scientific research in the field. But the success of CubeSat\u27s mission often fails. Improvements in reliability and prevent poor workmanship are necessary. The CubeSat standard enabled the small satellite market to expand enormously. In fact, a modular spacecraft deployer which can be attached to many different launch vehicles as a secondary payload was the key technology for the CubeSat Standard. To date, only external CubeSat interfaces, especially the mechanical interface, have been standardized. CubeSat needs a standardized internal interface to take advantage of the modularity. It will contribute to cost reduction and development time. One key to cutting costs and delivery time is a standardized internal interface for different CubeSat missions. In three CubeSat projects at the Kyushu Institute of Technology in Kyutech, a backplane interface approach, proposed as UWE-3 by the University of Würzburg in Germany, has been implemented to reduce the time for development and assembly. The backplane approach also helped to reduce the risk of harnessing faults. In order to satisfy the mission requirements, however, modifications to the proposed standard interface board were necessary for each CubeSat project. The thesis proposes a new idea of a Software-Configurable Bus Interface (SoftCIB) with a backplane board to obtain more flexibility, particularly for data connections. Instead of hardware routing, a Complex Programmable Logical Device (CPLD) was used to reprogram the bus interface on the PCB. The following advantages will be offered by the standardized backplane interface board: (1) less harness, (2) ease of assembly and disassembly (3) compatible with different CubeSat projects and (4) flexible for routings. We can use the SoftCIB again to reduce the cost and development of the interface boards, rather than designing and making new interface boards for new CubeSat projects. Various projects have various payloads for missions and interface requirements. The high flexibility of SoftCIB\u27s interface allows one to select either the same or a different subsystem board such as an OBC or EPS. A functional test with a breadboard module validated the concept. A radiation test has shown that the selected CPLD is strong enough to maintain total ionization doses in low Earth orbit of more than 2 years. The system level verification has been carried out in the engineering model of the BIRDS-3 project at Kyutech.九州工業大学博士学位論文 学位記番号:工博甲第485号 学位授与年月日:令和元年9月20日1. Introduction|2. Background|3. Implementation of Backplane approach for CubeSats|4. Purposed interface – The SoftCIB|5. Testing campaign|6. On-orbit demonstration|7. Conclusions九州工業大学令和元年

    A Demonstrator for the ATLAS Level-1 Muon to Central Trigger Processor Interface (MUCTPI)

    Get PDF
    The Level-1 Muon Trigger Interface (MUCTPI) to the Central Trigger Processor (CTP) receives trigger information from the detector- specific logic of the muon trigger. This information contains up to two muon-track candidates per sector. The MUCTPI combines the information of all sectors and calculates total multiplicity values for each of six programmable pT thresholds. It avoids double counting of single muons by taking into account the fact that some of the trigger sectors overlap. The MUCTPI sends the multiplicity values to the CTP which takes the final Level-1 decision. For every Level-1 Accept (L1A) the MUCTPI sends region-of-interest (RoI) information to the Level-2 trigger and event data to the data acquisition system. A demonstrator of the MUCTPI has been built which has the performance of the final system but has limited flexibility for calculating the overlap. The functionality and the performance of the demonstrator are presented

    Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 1: Army fault tolerant architecture overview

    Get PDF
    Digital computing systems needed for Army programs such as the Computer-Aided Low Altitude Helicopter Flight Program and the Armored Systems Modernization (ASM) vehicles may be characterized by high computational throughput and input/output bandwidth, hard real-time response, high reliability and availability, and maintainability, testability, and producibility requirements. In addition, such a system should be affordable to produce, procure, maintain, and upgrade. To address these needs, the Army Fault Tolerant Architecture (AFTA) is being designed and constructed under a three-year program comprised of a conceptual study, detailed design and fabrication, and demonstration and validation phases. Described here are the results of the conceptual study phase of the AFTA development. Given here is an introduction to the AFTA program, its objectives, and key elements of its technical approach. A format is designed for representing mission requirements in a manner suitable for first order AFTA sizing and analysis, followed by a discussion of the current state of mission requirements acquisition for the targeted Army missions. An overview is given of AFTA's architectural theory of operation
    corecore