Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation

This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated

Semiconductor Device Modeling and Simulation for Electronic Circuit Design

This chapter covers different methods of semiconductor device modeling for electronic circuit simulation. It presents a discussion on physics-based analytical modeling approach to predict device operation at specific conditions such as applied bias (e.g., voltages and currents); environment (e.g., temperature, noise); and physical characteristics (e.g., geometry, doping levels). However, formulation of device model involves trade-off between accuracy and computational speed and for most practical operation such as for SPICE-based circuit simulator, empirical modeling approach is often preferred. Thus, this chapter also covers empirical modeling approaches to predict device operation by implementing mathematically fitted equations. In addition, it includes numerical device modeling approaches, which involve numerical device simulation using different types of commercial computer-based tools. Numerical models are used as virtual environment for device optimization under different conditions and the results can be used to validate the simulation models for other operating conditions

Statistical compact model strategies for nano CMOS transistors subject of atomic scale variability

One of the major limiting factors of the CMOS device, circuit and system simulation in sub 100nm regimes is the statistical variability introduced by the discreteness of charge and granularity of matter. The statistical variability cannot be eliminated by tuning the layout or by tightening fabrication process control. Since the compact models are the key bridge between technology and design, it is necessary to transfer reliably the MOSFET statistical variability information into compact models to facilitate variability aware design practice. The aim of this project is the development of a statistical extraction methodology essential to capture statistical variability with optimum set of parameters particularly in industry standard compact model BSIM. This task is accomplished by using a detailed study on the sensitivity analysis of the transistor current in respect to key parameters in compact model in combination with error analysis of the fitted Id-Vg characteristics. The key point in the developed direct statistical compact model strategy is that the impacts of statistical variability can be captured in device characteristics by tuning a limited number of parameters and keeping the values for remaining major set equal to their default values obtained from the “uniform” MOSFET compact model extraction. However, the statistical compact model extraction strategies will accurately represent the distribution and correlation of the electrical MOSFET figures of merit. Statistical compact model parameters are generated using statistical parameter generation techniques such as uncorrelated parameter distributions, principal component analysis and nonlinear power method. The accuracy of these methods is evaluated in comparison with the results obtained from ‘atomistic’ simulations. The impact of the correlations in the compact model parameters has been analyzed along with the corresponding transistor figures of merit. The accuracy of the circuit simulations with different statistical compact model libraries has been studied. Moreover, the impact of the MOSFET width/length on the statistical trend of the optimum set of statistical compact model parameters and electrical figures of merit has been analyzed with two methods to capture geometry dependencies in proposed statistical models

A Study on SPICE Modeling of Non-Resonant Plasmonic Terahertz Detector

Department Of Electrical EngineeringThe terahertz (sub-millimeter wave) is the frequency resource, ranging from 100 GHz ~ 10 THz band, located in the middle region of the infrared and millimeter waves in the electromagnetic spectrum. Terahertz waves has unique physical characteristics, which is transparency of radio waves and straightness of light waves, simultaneously. The terahertz wave is applied to the basic science, such as device, spectroscopy, and imaging technology. And also adjust in the applied science, such as biomedical engineering, security, environment, information and communication. Which importance already verified. In the new shape of future market is expected to be formed broadly. For this application, operating in the THz frequency detecting device essential. Recently, Current elements operating in terahertz are present, such as compound semiconductor (???-???HBT, HEMT). But, there are disadvantage to use as a high price. Therefore, research have been made of silicon based THz detector in many research groups. Silicon-based nano-technology utilizes a plasma wave transistor technology. Which is using the space-time change of the channel charge density. That causes plasma wave oscillation in the MOSFET (Metal oxide semiconductor field effect transistor) channel and this effect available MOSET operating terahertz regime beyond MOSFET cut-off frequency. So, PWT (plasma wave transistor) is available terahertz detection and oscillation. For integrated possible post processing circuit development in these of terahertz applications system, silicon based PWT compact model is essential thing. For this compact model for spice simulation beyond cut-off frequency, we consider charge time variance model which is NQS (non-quasi-static) model, not quasi-static model. For NQS model two kinds of model exist, first is RC ladder model. That is seral connect MOSFET get rid of parasitic elements. And these complex circuit making the equivalent circuit model, it called New Elmore model. For post processing circuit simulation, fast simulation speed is essential, RC ladder model has a disadvantage (for simulating each segment). In this thesis we using New Elmore model based on Non-resonant plasmonic THz detector modeling, And verified physical validity of our NQS model using the our TCAD model based on Quasi-plasma 2DEG. And we propose fast and accurate compact modelingope

A Study on SPICE Modeling of Non-Resonant Plasmonic Terahertz Detector

Department Of Electrical EngineeringThe terahertz (sub-millimeter wave) is the frequency resource, ranging from 100 GHz ~ 10 THz band, located in the middle region of the infrared and millimeter waves in the electromagnetic spectrum. Terahertz waves has unique physical characteristics, which is transparency of radio waves and straightness of light waves, simultaneously. The terahertz wave is applied to the basic science, such as device, spectroscopy, and imaging technology. And also adjust in the applied science, such as biomedical engineering, security, environment, information and communication. Which importance already verified. In the new shape of future market is expected to be formed broadly. For this application, operating in the THz frequency detecting device essential. Recently, Current elements operating in terahertz are present, such as compound semiconductor (???-???HBT, HEMT). But, there are disadvantage to use as a high price. Therefore, research have been made of silicon based THz detector in many research groups. Silicon-based nano-technology utilizes a plasma wave transistor technology. Which is using the space-time change of the channel charge density. That causes plasma wave oscillation in the MOSFET (Metal oxide semiconductor field effect transistor) channel and this effect available MOSET operating terahertz regime beyond MOSFET cut-off frequency. So, PWT (plasma wave transistor) is available terahertz detection and oscillation. For integrated possible post processing circuit development in these of terahertz applications system, silicon based PWT compact model is essential thing. For this compact model for spice simulation beyond cut-off frequency, we consider charge time variance model which is NQS (non-quasi-static) model, not quasi-static model. For NQS model two kinds of model exist, first is RC ladder model. That is seral connect MOSFET get rid of parasitic elements. And these complex circuit making the equivalent circuit model, it called New Elmore model. For post processing circuit simulation, fast simulation speed is essential, RC ladder model has a disadvantage (for simulating each segment). In this thesis we using New Elmore model based on Non-resonant plasmonic THz detector modeling, And verified physical validity of our NQS model using the our TCAD model based on Quasi-plasma 2DEG. And we propose fast and accurate compact modelingope

An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits

In this paper, we present the first validation of the virtual source (VS) charge-based compact model for standard cell libraries and large-scale digital circuits. With only a modest number of physically meaningful parameters, the VS model accounts for the main short-channel effects in nanometer technologies. Using a novel DC and transient parameter extraction methodology, the model is verified with simulated data from a well-characterized, industrial 40-nm bulk silicon model. The VS model is used to fully characterize a standard cell library with timing comparisons showing less than 2.7% error with respect to the industrial design kit. Furthermore, a 1001-stage inverter chain and a 32-bit ripple-carry adder are employed as test cases in a vendor CAD environment to validate the use of the VS model for large-scale digital circuit applications. Parametric Vdd sweeps show that the VS model is also ready for usage in low-power design methodologies. Finally, runtime comparisons have shown that the use of the VS model results in a speedup of about 7.6×.Masdar Institute of Science and Technology (Massachusetts Institute of Technology Cooperative Agreement

Statistical Modeling with the Virtual Source MOSFET Model

A statistical extension of the ultra-compact Virtual Source (VS) MOSFET model is developed here for the first time. The characterization uses a statistical extraction technique based on the backward propagation of variance (BPV) with variability parameters derived directly from the nominal VS model. The resulting statistical VS model is extensively validated using Monte Carlo simulations, and the statistical distributions of several figures of merit for logic and memory cells are compared with those of a BSIM model from a 40-nm CMOS industrial design kit. The comparisons show almost identical distributions with distinct run time advantages for the statistical VS model. Additional simulations show that the statistical VS model accurately captures non-Gaussian features that are important for low-power designs.Masdar Institute of Science and Technolog

Investigation into digital circuit design with GaAs/Ga2O3 heterostructure MOSFETs

In this thesis, GaAs heterostructure MOSFETs are investigated as a potential technology for digital circuit design. The devices under investigation are 0.6 μm gate length, enhancement mode, heterostructure MOSFETs, with a high-κ dielectric (Ga2O3), and an InGaAs channel. Historically silicon CMOS technology has been the natural choice for digital circuits, however the realisation of GaAs MOSFET digital circuits could allow full integration of RF, optoelectronic and digital circuits on a single system-on-chip. Additionally, there are potential performance advantages in using GaAs due to it's high electron mobility. For the first time compact models of complimentary GaAs/Ga2O3 MOS are developed to enable an investigation into establishing a digital design methodology for GaAs MOS. Drift-diffusion models are developed and calibrated to measured device data. These models then provide information on the necessary device parameters to build compact models of these devices. BSIM3v3.2 compact models are developed based on this to enable GaAs MOS technology to be investigated using standard circuit design tools. The compact models have been adapted to ensure that they are physically relevant for GaAs devices. This includes some necessary approximations using effective medium theory. Further adjustments, or ratio corrections, are introduced to ensure that the internal physical parameters of BSIM will be correct. The models are compared to similarly-sized silicon devices to investigate the difference in performance between GaAs and silicon MOSFETs. As expected, the GaAs NMOS devices demonstrate improvements in drive current over silicon. However, the GaAs PMOS devices do not offer this advantage due to low hole mobility. Therefore, as a consequence of the high mobility ratio in GaAs, it is important to consider alternative digital design methodologies to CMOS to optimise performance. The performance of benchmark circuits is investigated for this technology in various digital design styles including CMOS, NMOS saturated enhancement load, and NMOS precharge. GaAs digital circuits gain a signifcant advantage in using alternative design styles to CMOS due to the relatively poor performance of the PMOS devices. In using the alternative styles the number of PMOS devices used can be minimised, and it is shown that NMOS precharge offers both speed and power advantages for this technology. The particular GaAs technology investigated does not outperform silicon in terms of speed and power. However, it has allowed a methodology to be established for future device generations, where performance is anticipated to improve signifcantly