16 research outputs found
Self-Test Mechanisms for Automotive Multi-Processor System-on-Chips
L'abstract è presente nell'allegato / the abstract is in the attachmen
The ABC130 barrel module prototyping programme for the ATLAS strip tracker
For the Phase-II Upgrade of the ATLAS Detector, its Inner Detector,
consisting of silicon pixel, silicon strip and transition radiation
sub-detectors, will be replaced with an all new 100 % silicon tracker, composed
of a pixel tracker at inner radii and a strip tracker at outer radii. The
future ATLAS strip tracker will include 11,000 silicon sensor modules in the
central region (barrel) and 7,000 modules in the forward region (end-caps),
which are foreseen to be constructed over a period of 3.5 years. The
construction of each module consists of a series of assembly and quality
control steps, which were engineered to be identical for all production sites.
In order to develop the tooling and procedures for assembly and testing of
these modules, two series of major prototyping programs were conducted: an
early program using readout chips designed using a 250 nm fabrication process
(ABCN-25) and a subsequent program using a follow-up chip set made using 130 nm
processing (ABC130 and HCC130 chips). This second generation of readout chips
was used for an extensive prototyping program that produced around 100
barrel-type modules and contributed significantly to the development of the
final module layout. This paper gives an overview of the components used in
ABC130 barrel modules, their assembly procedure and findings resulting from
their tests.Comment: 82 pages, 66 figure
A Survey on Security Threats and Countermeasures in IEEE Test Standards
International audienceEditor's note: Test infrastructure has been shown to be a portal for hackers. This article reviews the threats and countermeasures for IEEE test infrastructure standards
Tester for chosen sub-standard of the IEEE 802.1Q
Tato práce se zabĂ˝vá analyzovánĂm IEEE 802.1Q standardu TSN skupiny a návrhem testovacĂho modulu. TestovacĂ modul je napsán v jazyku VHDL a je moĹľnĂ© jej implementovat do Intel Stratix® V GX FPGA (5SGXEA7N2F45C2) vĂ˝vojovĂ© desky. Standard IEEE 802.1Q (TSN) definuje deterministickou komunikace pĹ™es Ethernet sĂt, v reálnĂ©m ÄŤase, poĹľĂvánĂm globálnĂho ÄŤasu a správnĂ˝m rozvrhem vysĂlánĂm a pĹ™Ăjmem zpráv. HlavnĂ funkce tohoto standardu jsou: ÄŤasová synchronizace, plánovánĂ provozu a konfigurace sĂtÄ›. KaĹľdá z tÄ›chto funkcĂ je definovaná pomocĂ vĂce rĹŻznĂ˝ch podskupin tohoto standardu. Podle definice IEEE 802.1Q standardu je moĹľno tyto podskupiny vzájemnÄ› libovolnÄ› kombinovat. NÄ›kterĂ© podskupiny standardu nemohou fungovat nezávisle, musĂ vyuĹľĂvat funkce jinĂ˝ch podskupin standardu. Realizace funkce podskupin standardu je moĹľná softwarovÄ›, hardwarovÄ›, nebo jejich kombinacĂ. Na základÄ› výše uvedenĂ˝ch fakt, implementace podskupin standardu, kterĂ© jsou softwarovÄ› souvisejĂcĂ, byly vylouÄŤenĂ©. Taky byly vylouÄŤenĂ© podskupiny standardĹŻ, kterĂ© jsou závislĂ© na jinĂ˝ch podskupinách. IEEE 802.1Qbu byl vybrán jako vhodná část pro realizaci hardwarovĂ©ho testu. RĹŻznĂ© zpĹŻsoby testovánĂ byly vysvÄ›tleny jako DFT, BIST, ATPG a dalšà jinĂ© techniky. Pro hardwarovĂ© testovánĂ byla vybrána „Protocol Aware (PA)“technika, protoĹľe tato technika zrychluje testovánĂ, dovoluje opakovanou pouĹľitelnost a taky zkracuje dobu uvedenĂ na trh. TestovacĂ modul se skládá ze dvou objektĹŻ (generátor a monitor), kterĂ© majĂ implementovanou IEEE 802.1Qbu podskupinu standardu. Funkce generátoru je vygenerovat náhodnĂ© nebo nenáhodnĂ© impulzy a potom je poslat do testovanĂ©ho zaĹ™Ăzeni ve správnĂ©m definovanĂ©m protokolu. Funkce monitoru je pĹ™ijat ethernet rámce a ověřit jejich správnost. Objekty jsou navrhnuty stejnĂ˝m zpĹŻsobem na „TOP“úrovni a skládajĂ se ze ÄŤtyĹ™ modulĹŻ: Avalon MM rozhranĂ, dvou šablon a jednoho portu. Avalon MM rozhranĂ bylo vytvoĹ™eno pro komunikaci softwaru s hardwarem. Tento modul pĹ™ijme pakety ze softwaru a potom je dekĂłduje podle definovanĂ©ho protokolu a „pod-protokolu “. „Pod-protokol“se skládá z pĹ™Ăkazu a hodnoty danĂ©ho pĹ™Ăkazu. Podle dekĂłdovanĂ©ho pĹ™Ăkazu a hodnot danĂ˝ch pĹ™Ăkazem je kontrolovanĂ˝ celĂ˝ objekt. Ĺ ablona se pouĹľĂvá na generovánĂ nebo ověřovánĂ náhodnĂ˝ch nebo nenáhodnĂ˝ch dat. DvÄ› šablony byly implementovány pro expresnĂ ověřovánĂ nebo preempÄŤnĂ transakce, definovanĂ© IEEE 802.1Qbu. Porty byly vytvoĹ™enĂ© pro komunikaci mezi testovanĂ˝m zaĹ™ĂzenĂm a šablonou podle danĂ©ho standardu. Port „generátor“má za Ăşkol vybrat a vyslat rámce podle priority a ÄŤasu vysĂlanĂ. Port „monitor“pĹ™ijme rámce do „content-addressable memory”, která ověřuje priority rámce a podle toho je posĂlá do správnĂ© šablony. VĂ˝sledky prokázaly, Ĺľe tato testovacĂ technika dosahuje vysokĂ© rychlosti a rychlĂ© implementace.This master paper is dealing with the analysis of IEEE 802.1Q group of TSN standards and with the design of HW tester. Standard IEEE 802.1Qbu has appeared to be an optimal solution for this paper. Detail explanation of this sub-standard are included in this paper. As HW test the implementation, a protocol aware technique was chosen in order to accelerate testing. Paper further describes architecture of this tester, with detail explanation of the modules. Essential issue of protocol aware controlling objects by SW, have been resolved and described. Result proof that this technique has reached higher speed of testing, reusability, and fast implementation.
New techniques for functional testing of microprocessor based systems
Electronic devices may be affected by failures, for example due to physical defects. These defects may be introduced during the manufacturing process, as well as during the normal operating life of the device due to aging. How to detect all these defects is not a trivial task, especially in complex systems such as processor cores. Nevertheless, safety-critical applications do not tolerate failures, this is the reason why testing such devices is needed so to guarantee a correct behavior at any time. Moreover, testing is a key parameter for assessing the quality of a manufactured product.
Consolidated testing techniques are based on special Design for Testability (DfT) features added in the original design to facilitate test effectiveness. Design, integration, and usage of the available DfT for testing purposes are fully supported by commercial EDA tools, hence approaches based on DfT are the standard solutions adopted by silicon vendors for testing their devices.
Tests exploiting the available DfT such as scan-chains manipulate the internal state of the system, differently to the normal functional mode, passing through unreachable configurations. Alternative solutions that do not violate such functional mode are defined as functional tests.
In microprocessor based systems, functional testing techniques include software-based self-test (SBST), i.e., a piece of software (referred to as test program) which is uploaded in the system available memory and executed, with the purpose of exciting a specific part of the system and observing the effects of possible defects affecting it. SBST has been widely-studies by the research community for years, but its adoption by the industry is quite recent.
My research activities have been mainly focused on the industrial perspective of SBST. The problem of providing an effective development flow and guidelines for integrating SBST in the available operating systems have been tackled and results have been provided on microprocessor based systems for the automotive domain. Remarkably, new algorithms have been also introduced with respect to state-of-the-art approaches, which can be systematically implemented to enrich SBST suites of test programs for modern microprocessor based systems. The proposed development flow and algorithms are being currently employed in real electronic control units for automotive products.
Moreover, a special hardware infrastructure purposely embedded in modern devices for interconnecting the numerous on-board instruments has been interest of my research as well. This solution is known as reconfigurable scan networks (RSNs) and its practical adoption is growing fast as new standards have been created. Test and diagnosis methodologies have been proposed targeting specific RSN features, aimed at checking whether the reconfigurability of such networks has not been corrupted by defects and, in this case, at identifying the defective elements of the network. The contribution of my work in this field has also been included in the first suite of public-domain benchmark networks
Innovative Techniques for Testing and Diagnosing SoCs
We rely upon the continued functioning of many electronic devices for our everyday welfare,
usually embedding integrated circuits that are becoming even cheaper and smaller
with improved features. Nowadays, microelectronics can integrate a working computer
with CPU, memories, and even GPUs on a single die, namely System-On-Chip (SoC).
SoCs are also employed on automotive safety-critical applications, but need to be tested
thoroughly to comply with reliability standards, in particular the ISO26262 functional
safety for road vehicles.
The goal of this PhD. thesis is to improve SoC reliability by proposing innovative
techniques for testing and diagnosing its internal modules: CPUs, memories, peripherals,
and GPUs. The proposed approaches in the sequence appearing in this thesis are described
as follows:
1. Embedded Memory Diagnosis: Memories are dense and complex circuits which
are susceptible to design and manufacturing errors. Hence, it is important to understand
the fault occurrence in the memory array. In practice, the logical and physical
array representation differs due to an optimized design which adds enhancements to
the device, namely scrambling. This part proposes an accurate memory diagnosis
by showing the efforts of a software tool able to analyze test results, unscramble
the memory array, map failing syndromes to cell locations, elaborate cumulative
analysis, and elaborate a final fault model hypothesis. Several SRAM memory failing
syndromes were analyzed as case studies gathered on an industrial automotive
32-bit SoC developed by STMicroelectronics. The tool displayed defects virtually,
and results were confirmed by real photos taken from a microscope.
2. Functional Test Pattern Generation: The key for a successful test is the pattern applied
to the device. They can be structural or functional; the former usually benefits
from embedded test modules targeting manufacturing errors and is only effective
before shipping the component to the client. The latter, on the other hand, can be
applied during mission minimally impacting on performance but is penalized due
to high generation time. However, functional test patterns may benefit for having
different goals in functional mission mode. Part III of this PhD thesis proposes
three different functional test pattern generation methods for CPU cores embedded
in SoCs, targeting different test purposes, described as follows:
a. Functional Stress Patterns: Are suitable for optimizing functional stress during
I
Operational-life Tests and Burn-in Screening for an optimal device reliability
characterization
b. Functional Power Hungry Patterns: Are suitable for determining functional
peak power for strictly limiting the power of structural patterns during manufacturing
tests, thus reducing premature device over-kill while delivering high test
coverage
c. Software-Based Self-Test Patterns: Combines the potentiality of structural patterns
with functional ones, allowing its execution periodically during mission.
In addition, an external hardware communicating with a devised SBST was proposed.
It helps increasing in 3% the fault coverage by testing critical Hardly
Functionally Testable Faults not covered by conventional SBST patterns.
An automatic functional test pattern generation exploiting an evolutionary algorithm
maximizing metrics related to stress, power, and fault coverage was employed
in the above-mentioned approaches to quickly generate the desired patterns. The
approaches were evaluated on two industrial cases developed by STMicroelectronics;
8051-based and a 32-bit Power Architecture SoCs. Results show that generation
time was reduced upto 75% in comparison to older methodologies while
increasing significantly the desired metrics.
3. Fault Injection in GPGPU: Fault injection mechanisms in semiconductor devices
are suitable for generating structural patterns, testing and activating mitigation techniques,
and validating robust hardware and software applications. GPGPUs are
known for fast parallel computation used in high performance computing and advanced
driver assistance where reliability is the key point. Moreover, GPGPU manufacturers
do not provide design description code due to content secrecy. Therefore,
commercial fault injectors using the GPGPU model is unfeasible, making radiation
tests the only resource available, but are costly. In the last part of this thesis, we
propose a software implemented fault injector able to inject bit-flip in memory elements
of a real GPGPU. It exploits a software debugger tool and combines the
C-CUDA grammar to wisely determine fault spots and apply bit-flip operations in
program variables. The goal is to validate robust parallel algorithms by studying
fault propagation or activating redundancy mechanisms they possibly embed. The
effectiveness of the tool was evaluated on two robust applications: redundant parallel
matrix multiplication and floating point Fast Fourier Transform
Test and Diagnosis of Integrated Circuits
The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users, the manufacturing process is becoming finer and denser, making chips more prone to defects.The work presented in the HDR manuscript addresses the challenges of test and diagnosis of integrated circuits. It covers:- Power aware test;- Test of Low Power Devices;- Fault Diagnosis of digital circuits
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
<p>As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects</p><p>have become the dominant contributor to circuit delay and a significant component of</p><p>power consumption. In order to reduce the length of these interconnects, 3D integration</p><p>and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry.</p><p>3D SICs not only have the potential to reduce average interconnect length and alleviate</p><p>many of the problems caused by long global interconnects, but they can offer greater design</p><p>flexibility over 2D ICs, significant reductions in power consumption and footprint in</p><p>an era of mobile applications, increased on-chip data bandwidth through delay reduction,</p><p>and improved heterogeneous integration.</p><p>Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.</p><p>Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a</p><p>die stack, are a source of additional and unique defects not seen before in ICs. At the same</p><p>time, testing these TSVs, especially before die stacking, is recognized as a major challenge.</p><p>The testing of a 3D stack is constrained by limited test access, test pin availability,</p><p>power, and thermal constraints. Therefore, efficient and optimized test architectures are</p><p>needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively</p><p>expensive.</p><p>Methods of testing TSVs prior to bonding continue to be a difficult problem due to test</p><p>access and testability issues. Although some built-in self-test (BIST) techniques have been</p><p>proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through</p><p>TSV probing. This has the benefit of not needing large analog test components on the die,</p><p>which is a significant drawback of many BIST architectures. Coupled with an optimization</p><p>method described in this dissertation to create parallel test groups for TSVs, test time for</p><p>pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is</p><p>expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and</p><p>structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.</p><p>The addition of boundary registers on functional TSV paths required for pre-bond</p><p>probing results in an increase in delay on inter-die functional paths. This cost of test</p><p>architecture insertion can be a significant drawback, especially considering that one benefit</p><p>of 3D integration is that critical paths can be partitioned between dies to reduce their delay.</p><p>This dissertation derives a retiming flow that is used to recover the additional delay added</p><p>to TSV paths by test cell insertion.</p><p>Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary</p><p>during 3D-SIC manufacturing. To reduce test cost, the test architecture and test</p><p>scheduling for the stack must be optimized to reduce test time across all necessary test</p><p>insertions. This dissertation examines three paradigms for 3D integration - hard dies, firm</p><p>dies, and soft dies, that give varying degrees of control over 2D test architectures on each</p><p>die while optimizing the 3D test architecture. Integer linear programming models are developed</p><p>to provide an optimal 3D test architecture and test schedule for the dies in the 3D</p><p>stack considering any or all post-bond test insertions. Results show that the ILP models</p><p>outperform other optimization methods across a range of 3D benchmark circuits.</p><p>In summary, this dissertation targets testing and design-for-test (DFT) of 3D SICs.</p><p>The proposed techniques enable pre-bond TSV and structural test while maintaining a</p><p>relatively low test cost. Future work will continue to enable testing of 3D SICs to move</p><p>industry closer to realizing the true potential of 3D integration.</p>Dissertatio