Discriminator logics (Research announcement)

A discriminator logic is the 1-assertional logic of a discriminator variety V having two constant terms 0 and 1 such that V ⊨ 0 1 iff every member of V is trivial. Examples of such logics abound in the literature. The main result of this research announcement asserts that a certain non-Fregean deductive system SBPC, which closely resembles the classical propositional calculus, is canonical for the class of discriminator logics in the sense that any discriminator logic S can be presented (up to definitional equivalence) as an axiomatic extension of SBPC by a set of extensional logical connectives taken from the language of S. The results outlined in this research announcement are extended to several generalisations of the class of discriminator logics in the main work

Discriminator logics (Research announcement)

A discriminator logic is the 1-assertional logic of a discriminator variety V having two constant terms 0 and 1 such that V ⊨ 0 1 iff every member of V is trivial. Examples of such logics abound in the literature. The main result of this research announcement asserts that a certain non-Fregean deductive system SBPC, which closely resembles the classical propositional calculus, is canonical for the class of discriminator logics in the sense that any discriminator logic S can be presented (up to definitional equivalence) as an axiomatic extension of SBPC by a set of extensional logical connectives taken from the language of S. The results outlined in this research announcement are extended to several generalisations of the class of discriminator logics in the main work

Factor Varieties and Symbolic Computation

We propose an algebraization of classical and non-classical logics, based on factor varieties and decomposition operators. In particular, we provide a new method for determining whether a propositional formula is a tautology or a contradiction. This method can be autom-atized by defining a term rewriting system that enjoys confluence and strong normalization. This also suggests an original notion of logical gate and circuit, where propositional variables becomes logical gates and logical operations are implemented by substitution. Concerning formulas with quantifiers, we present a simple algorithm based on factor varieties for reducing first-order classical logic to equational logic. We achieve a completeness result for first-order classical logic without requiring any additional structure

Formal verification of a fault tolerant clock synchronization algorithm

A formal specification and mechanically assisted verification of the interactive convergence clock synchronization algorithm of Lamport and Melliar-Smith is described. Several technical flaws in the analysis given by Lamport and Melliar-Smith were discovered, even though their presentation is unusally precise and detailed. It seems that these flaws were not detected by informal peer scrutiny. The flaws are discussed and a revised presentation of the analysis is given that not only corrects the flaws but is also more precise and easier to follow. Some of the corrections to the flaws require slight modifications to the original assumptions underlying the algorithm and to the constraints on its parameters, and thus change the external specifications of the algorithm. The formal analysis of the interactive convergence clock synchronization algorithm was performed using the Enhanced Hierarchical Development Methodology (EHDM) formal specification and verification environment. This application of EHDM provides a demonstration of some of the capabilities of the system