Design Considerations of a Sub-50 {\mu}W Receiver Front-end for Implantable Devices in MedRadio Band

Emerging health-monitor applications, such as information transmission through multi-channel neural implants, image and video communication from inside the body etc., calls for ultra-low active power (<50${\mu}$W) high data-rate, energy-scalable, highly energy-efficient (pJ/bit) radios. Previous literature has strongly focused on low average power duty-cycled radios or low power but low-date radios. In this paper, we investigate power performance trade-off of each front-end component in a conventional radio including active matching, down-conversion and RF/IF amplification and prioritize them based on highest performance/energy metric. The analysis reveals 50${\Omega}$ active matching and RF gain is prohibitive for 50${\mu}$W power-budget. A mixer-first architecture with an N-path mixer and a self-biased inverter based baseband LNA, designed in TSMC 65nm technology show that sub 50${\mu}$W performance can be achieved up to 10Mbps (< 5pJ/b) with OOK modulation.Comment: Accepted to appear on International Conference on VLSI Design 2018 (VLSID

Demonstration of a switchless Class E/Fodd dual-band power amplifier

A 250 W dual-band power amplifier belonging to the Class E/F switching amplifier family is presented. The amplifier operates in the 7 MHz and 10 MHz HAM bands, achieving 16 dB and 15 d B gain with power added efficiencies (PAE) of 92% and 87% in those bands, respectively. It utilizes dual-resonant passive input and output networks to achieve high-efficiency Class E/Fodd operation at both frequencies of operation, allowing the same passive networks to be used for both frequency bands without the use of band-select switches

Design and linearization of an efficient class E power amplifier using a test bench based on development boards

Nowadays, with the increase in small satellites applications for Earth observation, the need for high efficient transmitters capable of delivering the required power, taking into account not only the power consumption limitations of small satellites (solar powered), but also the required linearity to allow high data rates in the downlink, has fostered the research on alternatives to the classical transmitter amplification. This Master Thesis has the objective to mitigate the inherent trade-off between linearity and efficiency in communication transmitters by addressing the design of an efficient Power Amplifier (PA) combined with the implementation of Crest Factor Reduction (CFR) and Digital Predistortion (DPD) techniques. For this purpose, the deployment of a low-budget test bench based on development boards is proposed to carry out the PA evaluation and linearization avoiding the use of expensive laboratory equipment for signal generation and analysis. The experimental campaign was carried out using CFR technique to limit the Peak to Average Power Ratio (PAPR) in addition to the DPD linearization, this method not only allowed us to reduce spectral regrowth and minimize in-band distortion, but also was a crucial approach to maximize power amplifier efficiency fulfilling the linearity requirement imposed by the communications standards. The evaluation of the class-E PA designed (under the supervision of the Communication Engineering research group of the University of Cantabria) was performed using a LTE-like signal of 20 MHz employing Quadrature Amplitude Modulation (QAM) and Orthogonal Frequency-Division Multiplexing (OFDM). The measurements shown that it is possible to achieve an output power of 36,6 dBm with an efficiency about 50% in contrast to the typical class-AB PA efficiency figures ranging from 5-10% when operated with significant back-off levels to avoid saturation. Moreover, the Adjacent Channel Power Ratio (ACPR) is below -45 dB and the Error Vector Magnitude (EVM) is around 1,4% for a 64QAM signal in compliance with the communication standards

The digital predistorter goes multi-dimensional: DPD for concurrent multi-band envelope tracking and outphasing power amplifiers

Over at least the last two decades, digital predistortion (DPD) has become the most common and widespread solution to cope with the power amplifier's (PA's) inherent linearity-versus-efficiency tradeoff. When compared with other linearization techniques, such as Cartesian feedback or feedforward, DPD has proven able to adapt to the always-growing demands of technology: wider bandwidths, stringent spectrum masks, and reconfigurability. The principles of predistortion linearization (in its analog or digital forms) are straightforward, and the linearization subsystem precedes the PA (a nonlinear function in a digital signal processor in the case of DPD or nonlinear device in the case of analog predistortion and counteracts the nonlinear characteristic of the PA. Some excellent overviews on DPD can be found in [1]-[4]. Let us now look at the challenges that DPD linearization has faced and will continue to face in the near future with 5G new radio (5G-NR).This work has been supported in part by the Spanish Government and FEDER under MICINN projects TEC2017-83343-C4-1-R and TEC2017-83343-C4-2-R and by the Generalitat de Catalunya under Grant 2017 SGR 813

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

1.25 Gbit/s ITU-T G.984.2 burst-mode transimpedance amplifier without reset pins

A

III-V-on-silicon photonic devices for optical communication and sensing

In the paper, we review our work on heterogeneous III-V-on-silicon photonic components and circuits for applications in optical communication and sensing. We elaborate on the integration strategy and describe a broad range of devices realized on this platform covering a wavelength range from 850 nm to 3.85 μm