Decomposing balsa-STGs (working notes)

The DFG-project 'Optacon' is concerned with the resynthesis of speed-independentcircuits using STGs (a variant of Petri nets). One main issue is to decompose a large STG specifying the desired circuit behaviour into a collection of components that can be synthesized separately and together implement the specification. This report collects a number of working notes regarding useful decomposition; it assumes acquaintance with the topic

State-based encoding of large asynchronous controllers

State encoding is one of the fundamental problems in the synthesis of asynchronous controllers. The requirement for a correct hazard-free implementation imposes severe constraints on the way encoding signals can be inserted in the specification of a controller. Even though some specification formalisms, such as Burst-mode machines or Signal Transition Graphs, enable to specify behaviors at the event level, the state encoding methods that provide the best good-quality solutions work at the state level. This imposes a severe limitation on the size of the controllers that can be handled by these methods. This paper proposes a method to solve the encoding problem for large asynchronous controllers using statebased methods. It is based on an iterative process of projection and re-composition that reduces the size specification by hiding signals, partially solves the encoding problem at the state level and re-composes the original specification using a synchronous product. The process iterates until all encoding conflicts have been solved. The method is proved to preserve the behavior of the specification (branching bisimilarity) and shown to be capable of providing good-quality solutions for controllers of more than 100 signals and 106 states.Peer ReviewedPostprint (published version

Compositional circuit design with asynchronous concepts

PhD ThesisSynchronous circuits are pervasive in modern digital systems, such as smart-phones, wearable devices and computers. Synchronous circuits are controlled by a global clock signal, which greatly simplifies their design but is also a limitation in some applications. Asynchronous circuits are a logical alternative: they do not use a global clock to synchronise their components. Instead, every component reacts to input events at the rate they occur. Asynchronous circuits are not widely adopted by industry, because they are often harder to design and require more sophisticated tools and formal models. Signal Transition Graphs (STGs) is a well-studied formal model for the specification, verification and synthesis of asynchronous circuits with state-of-the-art tool support. STGs use a graphical notation where vertices and arcs specify the operation of an asynchronous circuit. These graphical specifications can be difficult to describe compositionally, and provide little reusability of useful sections of a graph. In this thesis we present Asynchronous Concepts, a new design methodology for asynchronous circuit design. A concept is a self-contained description of a circuit requirement, which is composable with any other concept, allowing compositional specification of large asynchronous circuits. Concepts can be shared, reused and extended by users, promoting the reuse of behaviours within single or multiple specifications. Asynchronous Concepts can be translated to STGs to benefit from the existing theory and tools developed by the asynchronous circuits community. Plato is a software tool developed for Asynchronous Concepts that supports the presented design methodology, and provides automated methods for translation to STGs. The design flow which utilises Asynchronous Concepts is automated using Plato and the open-source toolsuite Workcraft, which can use the translated STGs in verification and synthesis using integrated tools. The proposed language, the design flow, and the supporting tools are evaluated on real-world case studies

Is It Science Yet?: Intelligent Design Creationism and the Constitution

On several occasions during the last eighty years, states have attempted to either prohibit the teaching of evolution in public school science classes or counter the teaching of evolution with mandatory references to the religious doctrine of creationism. The Supreme Court struck down examples of the first two generations of these statutes, holding that they violated the Establishment Clause of the First Amendment. A third generation of creationist legislation is now being proposed. Under this new generation of creationism legislation, science teachers would present so-called “intelligent design” theory as an alternative to evolution. Intelligent design theory asserts that a supernatural intelligence intervened in the natural world to dictate the nature and ordering of all biological species, which do not evolve from lower-to higher-order beings. This article considers whether these intelligent design creationism proposals can survive constitutional scrutiny. The authors analyze the religious, philosophical, and scientific details of intelligent design theory, and assess these details in light of the constitutional doctrine developed by the Court in its previous creationism decisions. The Article discusses several factors that pose problems for intelligent design theory, including the absence of objective scientific support for intelligent design, evidence of strong links between intelligent design and religious doctrine, the use of intelligent design to limit the dissemination of scientific theories that are perceived as contradicting religious teachings, and the fact that the irreducible core of intelligent design theory is what the Court has called the “manifestly religious concept of a God or Supreme Being. Based on these details, the authors conclude that intelligent design theory cannot survive scrutiny under the constitutional framework used by the Court to invalidate earlier creationism mandates

Structural Decomposition of STGs

Specification of asynchronous circuit behaviour becomes more complex as the complexity of today’s System-On-a-Chip (SOC) design increases. This also causes the Signal Transition Graphs (STGs) – interpreted Petri nets for the specification of asynchronous circuit behaviour – to become bigger and more complex, which makes it more difficult, sometimes even impossible, to synthesize an asynchronous circuit from an STG with a tool like petrify [CKK+96] or CASCADE [BEW00]. It has, therefore, been suggested to decompose the STG as a first step; this leads to a modular implementation [KWVB03] [KVWB05], which can reduce syn- thesis effort by possibly avoiding state explosion or by allowing the use of library elements. A decomposition approach for STGs was presented in [VW02] [KKT93] [Chu87a]. The decomposition algorithm by Vogler and Wollowski [VW02] is based on that of Chu [Chu87a] but is much more generally applicable than the one in [KKT93] [Chu87a], and its correctness has been proved formally in [VW02]. This dissertation begins with Petri net background described in chapter 2. It starts with a class of Petri nets called a place/transition (P/T) nets. Then STGs, the subclass of P/T nets, is viewed. Background in net decomposition is presented in chapter 3. It begins with the structural decomposition of P/T nets for analysis purposes – liveness and boundedness of the net. Then STG decomposition for synthesis from [VW02] is described. The decomposition method from [VW02] still could be improved to deal with STGs from real applications and to give better decomposition results. Some improvements for [VW02] to improve decomposition result and increase algorithm efficiency are discussed in chapter 4. These improvement ideas are suggested in [KVWB04] and some of them are have been proved formally in [VK04]. The decomposition method from [VW02] is based on net reduction to find an output block component. A large amount of work has to be done to reduce an initial specification until the final component is found. This reduction is not always possible, which causes input initially classified as irrelevant to become relevant input for the component. But under certain conditions (e.g. if structural auto-conflicts turn out to be non-dynamic) some of them could be reclassified as irrelevant. If this is not done, the specifications become unnecessarily large, which intern leads to unnecessarily large implemented circuits. Instead of reduction, a new approach, presented in chapter 5, decomposes the original net into structural components first. An initial output block component is found by composing the structural components. Then, a final output block component is obtained by net reduction. As we cope with the structure of a net most of the time, it would be useful to have a structural abstraction of the net. A structural abstraction algorithm [Kan03] is presented in chapter 6. It can improve the performance in finding an output block component in most of the cases [War05] [Taw04]. Also, the structure net is in most cases smaller than the net itself. This increases the efficiency of the decomposition algorithm because it allows the transitions contained in a node of the structure graph to be contracted at the same time if the structure graph is used as internal representation of the net. Chapter 7 discusses the application of STG decomposition in asynchronous circuit design. Application to speed independent circuits is discussed first. Af- ter that 3D circuits synthesized from extended burst mode (XBM) specifications are discussed. An algorithm for translating STG specifications to XBM specifi- cations was first suggested by [BEW99]. This algorithm first derives the state machine from the STG specification, then translates the state machine to XBM specification. An XBM specification, though it is a state machine, allows some concurrency. These concurrencies can be translated directly, without deriving all of the possible states. An algorithm which directly translates STG to XBM specifications, is presented in chapter 7.3.1. Finally DESI, a tool to decompose STGs and its decomposition results are presented

Synthesis of variability-tolerant circuits with adaptive clocking

Improvements in circuit manufacturing have allowed, along the years, increasingly complex designs. This has been enabled by the miniaturization that circuit components have undergone. But, in recent years, this scaling has shown decreasing benefits as we approach fundamental limits. Furthermore, the decrease in size is nowadays producing an increase in variability: unpredictable differences and changes in the behavior of components. Historically, this has been addressed by establishing guardband margins at the design stage. Nonetheless, as variability grows, the amount of pessimism introduced by these margins is taking an ever-increasing cost on performance and power consumption. In recent years, several approaches have been proposed to lower the impact of variability and reduce margins. One such technique is the substitution of a classical PLL clock by a Ring Oscillator Clock. The design of the Ring Oscillator Clock is done in such a way that its variability is highly correlated to that of the circuit. One of the contributions of this thesis is in the automatic design of such circuits. In particular, we propose a novel method to design digital delay lines with variability-tracking properties. Those designs are also suitable for other purposes, such as bundled-data circuits or performance monitors. The advantage of the proposed technique is based on the exclusive use of cells from a standard cell library, which lowers the design cost and complexity. The other focus of this thesis is on state encoding for asynchronous controllers. One of the main properties of asynchronous circuits is their ability to, implicitly, work under variable conditions. In the near future, this advantage might increase the relevance of this class of circuits. One of the hardest stages for the synthesis of these circuits is the state encoding. This thesis presents a SAT-based algorithm for solving the state encoding at the state level. It is shown, by means of a comprehensive benchmark suite, that results obtained by this technique improve significantly compared to results from similar approaches. Nonetheless, the main limitation of techniques at the state level is the state explosion problem, to which the sequential modeling of concurrency is often subject to. The last contribution of this thesis is a method to process asynchronous circuits in order to allow the use of state-based techniques for large instances. In particular, the process is divided into three stages: projection, signal insertion and re-composition. In the projection step, the behavior of the controller is simplified until the signal insertion can be performed by state-based techniques. Afterwards, the re-composition generalizes the insertion of the signal into the original controller. Experimental results show that this process enables the resolution of large controllers, in the order of 10 6 states, by state-based techniques. At the same time, only a minor impact in solution quality is observed, preserving one of the main advantages for state-based approaches.A lo largo de los años, mejoras en la fabricación de circuitos han permitido diseños cada vez más complejos. Esta tendencia, que ha tenido lugar gracias a la miniaturización de los componentes que forman estos circuitos, recientemente está mostrando beneficios decrecientes a medida que nos acercamos a ciertas limitaciones fundamentales. Además de estos beneficios decrecientes, la reducción en tamaño está produciendo un aumento, cada vez mayor, en la variabilidad: diferencias impredecibles y cambios en el comportamiento de los componentes. Esto se ha compensado históricamente con el uso de márgenes de seguridad en la fase de diseño. No obstante, a medida que la variabilidad crece, la cantidad de pesimismo que estos márgenes introducen está afectando significativamente el coste en rendimiento y consumo energético. En los últimos años se han propuesto diferentes técnicas para limitar el impacto de la variabilidad y reducir márgenes de seguridad. Una de estas técnicas consiste en substituir un reloj PLL clásico por un Ring Oscillator Clock. El diseño de un Ring Oscillator Clock se realiza de manera que su variabilidad este altamente correlacionada con la del circuito. Una de las contribuciones de esta tesis consiste en el diseño automático de estos relojes. Concretamente, se propone un nuevo método para diseñar líneas de retardo digitales (digital delay lines) que tengan como propiedad la capacidad de imitar la variabilidad de un circuito dado. Estos diseños son también apropiados para otros propósitos, tal y como circuitos con ?bundled-data? o monitorizadores de rendimiento. La ventaja del método propuesto con respecto a otras técnicas similares radica en el uso exclusivo de celdas provenientes de una librería de celdas estándar, lo que reduce considerablemente el coste de diseño y su complejidad. Por otro lado, esta tesis también se centra en la codificación de estados de circuitos asíncronos. Una de las principales propiedades de estos circuitos reside en su capacidad implícita para trabajar bajo condiciones de variabilidad. Es previsible que, en un futuro próximo, esta ventaja se vuelva aún más relevante. La síntesis de circuitos asíncronos consta de varias etapas, una de las cuales es la codificación de estados. Este trabajo presenta un algoritmo basado en SAT que permite resolver la codificación de estados a nivel de estado. Mediante el uso de un exhaustivo banco de pruebas, esta tesis muestra como resultados obtenidos por esta técnica mejoran significativamente en comparación con otros métodos similares. A pesar de ello, técnicas que trabajan a nivel de estado tienen como principal limitación el problema conocido como "explosión de estados" que aparece habitualmente cuando se modelan elementos concurrentes de manera secuencial. Así pues, la última contribución de esta tesis es la propuesta de un método para procesar circuitos asíncronos de manera que técnicas a nivel de estado sean usables para instancias grandes. En concreto, el proceso está dividido en tres fases: proyección, inserción de señal y re-composición. En la etapa de proyección, el comportamiento del controlador es simplificado suficientemente como para que la inserción de la señal se pueda realizar con técnicas a nivel de estado. A continuación, la re-composición generaliza esta inserción en el controlador original. Resultados experimentales muestran que este proceso permite la resolución de grandes controladores, del orden de 10^6 estados, mediante el uso de técnicas a nivel de estado. Al mismo tiempo, solo se observa un impacto mínimo en la calidad de las soluciones, preservando una de las mayores ventajas de los métodos a nivel de estado

Evolving Minds: Helping Students with Cognitive Dissonance

Even 150 years after Charles Darwin published On the Origin of Species, public school teachers still find themselves dealing with student resistance to learning about biological evolution. Some teachers deal with this pressure by undermining, deemphasizing, or even omitting the topic in their science curriculum. Others face the challenge and deliver solid scientific instruction of evolutionary theory despite the conflicts that may arise. The latter were the topic of this study. I interviewed five teachers that had experience dealing with resistance to learning evolution in their school community. Through these in-depth interviews, I examined strategies these teachers use when facing resistance and how they help students deal with the cognitive dissonance that may be experienced when learning about evolution. I selected the qualitative method of educational criticism and connoisseurship to organize and categorize my data. From the interviews, the following findings emerged. Experienced teachers increased their confidence in teaching evolution by pursuing outside professional development. They not only learned more about evolutionary theory, but about creationist arguments against evolution. These teachers front-load their curriculum to integrate the nature of science into their lessons to address misunderstandings about how science works. They also highlight the importance of learning evolutionary theory but ensure students they do not have an agenda to indoctrinate students. Finally these experienced teachers work hard to create an intellectually safe learning environment to build trusting and respectful relationships with their students

Playing the Proof Game: Intelligent Design and the Law

Intelligent design advocates argue that excluding intelligent design from educational and scientific environments discriminates in favor of methodological naturalism and against other approaches for understanding natural phenomena. These arguments are flawed both legally and philosophically. In order to succeed ID advocates need to demonstrate that ID is science and that public school classes and scientific institutions are public fora for speech. Legal scholarship has generally ignored the most relevant arguments from philosophy of science and the relationship of those arguments to constitutional concepts. This article demonstrates that even when ID is given the benefit of the best scientific, philosophical, and legal arguments it is unequipped to take advantage. This is because, in part, ID is a response to several important cases decided under the Establishment Clause, and the form the ID movement has taken reflects a plan to avoid the legal defeats that creationism and creation science faced. Intelligent design is essentially a marketing plan to claim credibility in public discourse and to avoid conflict with inconvenient court decisions. At least as to the latter goal ID advocates are likely to fail

Darwinism, dichotomies and democracy: the rhetoric of intelligent design creationism

The Intelligent Design creationist movement seems to capture the interest of those who study rhetoric as a means to address one principal question: How can an argument so factually bankrupt as the neo-creationist narrative persuade so many people? This thesis is not an attempt to offer a comprehensive answer to this query, but instead to explore one of the many rhetorical devices employed by the Intelligent Design advocates themselves: the appeal to the either-or fallacy that suggests that all evidence against the position they seek to call into question (biological evolution) necessarily supports Intelligent Design. Logically, this argument can only claim cogency if there exist only two argumentative alternatives. As this is not the case (any number of alternatives besides Darwinian evolution and biblical creationism, or “Intelligent Design,” as it is now known, could be considered), Intelligent Design advocates simply structure their arguments to represent the idea that it is, in fact, the case; that rather than a range of possible explanations for the existence and diversity of life, the individual must choose between the present scientific explanations and the biblical explanation. This misrepresentation is disingenuous and deceptive, but it is also highly effective. Why? I will argue that the two-party democratic tradition in which the American citizen is raised trains her to see that: 1) There are two rather than many sides to a discussion; 2) The two positions are of relatively equal merit; and 3) Evidence against one position supports the other. The natural extension of this is that Intelligent Design creationists can win a debate simply by taking advantage of terms that present their arguments in a more favorable light than that for which there is factual warrant