Measurement, control and protection of microgrids at low frame rates supporting security of supply

Increasing penetrations of distributed generation at low power levels within electricity networks leads to the requirement for cheap, integrated, protection and control systems. To minimise unit cost, algorithms for the measurement of AC voltage and current waveforms should be implemented on a single microcontroller, which also carries out all other protection and control tasks, including communication and data logging. This limits the frame rate of the major algorithms, although ADCs can be over-sampled using peripheral control processors on suitable microcontrollers. Measurement algorithms also have to be tolerant of poor power quality which may arise, even transiently, within a microgrid, battlefield, or disaster-relief scenario. This thesis analyses the potential magnitude of these interfering signals, and presents suitably tolerant architectures and algorithms for measurements of AC waveforms (amplitude, phase and frequency). These algorithms are shown to be robust and accurate, with harmonic content up to the level of 53% THD, and with the major algorithms executing at only 500 samples per second. This is achieved by the careful optimisation and cascaded use of exact-time averaging techniques, which prove to be useful at all stages of the measurements: from DC bias removal to low-sample-rate Fourier analysis to sub-harmonic ripple removal. Algorithms for three-phase nodal power flow analysis are benchmarked on the Infineon TC1796 microcontroller and require less than 8% of the 2000μs frame time, leaving the remainder free for other algorithms. Furthermore, to optimise security of supply in a microgrid scenario, loss-of-mains must be detected quickly even when there is an accidental or deliberate balance between local active power generation and demand. The measurement techniques are extended to the detection of loss-of-mains using a new Phase Offset relay, in combination with a novel reactive power control technique to avoid the non-detection-zone. These techniques are tested using simulation, captured network transient events, and a real hardware microgrid including a synchronous generator and inverter

Efficient and Interference-Resilient Wireless Connectivity for IoT Applications

With the coming of age of the Internet of Things (IoT), demand on ultra-low power (ULP) and low-cost radios will continue to boost tremendously. The Bluetooth-Low-energy (BLE) standard provides a low power solution to connect IoT nodes with mobile devices, however, the power of maintaining a connection with a reasonable latency remains the limiting factor in defining the lifetime of event-driven BLE devices. BLE radio power consumption is in the milliwatt range and can be duty cycled for average powers around 30μW, but at the expense of long latency. Furthermore, wireless transceivers traditionally perform local oscillator (LO) calibration using an external crystal oscillator (XTAL) that adds significant size and cost to a system. Removing the XTAL enables a true single-chip radio, but an alternate means for calibrating the LO is required. Innovations in both the system architecture and circuits implementation are essential for the design of truly ubiquitous receivers for IoT applications. This research presents two porotypes as back-channel BLE receivers, which have lower power consumption while still being robust in the presents of interference and able to receive back-channel message from BLE compliant transmitters. In addition, the first crystal-less transmitter with symmetric over-the-air clock recovery compliant with the BLE standard using a GFSK-Modulated BLE Packet is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162942/1/abdulalg_1.pd

Models predicting the performance of IC component or PCB channel during electromagnetic interference

This dissertation is composed of three papers, which cover the prediction of the characteristics of jitter due to crosstalk and due to simultaneous switching noise, and covers susceptibility of delay locked loop (DLL) to electromagnetic interference. In the first paper, an improved tail-fit de-convolution method is proposed for characterizing the impact of deterministic jitter in the presence of random jitter. A Wiener filter de-convolution method is also presented for extracting the characteristics of crosstalk induced jitter from measurements of total jitter made when the crosstalk sources were and were not present. The proposed techniques are shown to work well both in simulations and in measurements of a high-speed link. In the second paper, methods are developed to predict the statistical distribution of timing jitter due to dynamic currents drawn by an integrated circuit (IC) and the resulting power supply noise on the PCB. Distribution of dynamic currents is found through vectorless methods. Results demonstrate the approach can rapidly determine the average and standard deviation of the power supply noise voltage and the peak jitter within 5~15% error, which is more than sufficient for predicting the performance impact on integrated circuits. In the third paper, a model is developed to predict the susceptibility of a DLL to electromagnetic noise on the power supply. With the proposed analytical noise transfer function, peak to peak jitter and cycle to cycle jitter at the DLL output can be estimated, which can be use to predict when soft failures will occur and to better understand how to fix these failures. Simulation and measurement results demonstrate the accuracy of the DLL delay model. --Abstract, page iv

On Borrowed Time -- Preventing Static Power Side-Channel Analysis

In recent years, static power side-channel analysis attacks have emerged as a serious threat to cryptographic implementations, overcoming state-of-the-art countermeasures against side-channel attacks. The continued down-scaling of semiconductor process technology, which results in an increase of the relative weight of static power in the total power budget of circuits, will only improve the viability of static power side-channel analysis attacks. Yet, despite the threat posed, limited work has been invested into mitigating this class of attack. In this work we address this gap. We observe that static power side-channel analysis relies on stopping the target circuit's clock over a prolonged period, during which the circuit holds secret information in its registers. We propose Borrowed Time, a countermeasure that hinders an attacker's ability to leverage such clock control. Borrowed Time detects a stopped clock and triggers a reset that wipes any registers containing sensitive intermediates, whose leakages would otherwise be exploitable. We demonstrate the effectiveness of our countermeasure by performing practical Correlation Power Analysis attacks under optimal conditions against an AES implementation on an FPGA target with and without our countermeasure in place. In the unprotected case, we can recover the entire secret key using traces from 1,500 encryptions. Under the same conditions, the protected implementation successfully prevents key recovery even with traces from 1,000,000 encryptions

CMOS Signal Synthesizers for Emerging RF-to-Optical Applications

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam

Power System Stability With a High Penetration of Inverter-Based Resources

Inverter-based resources (IBRs) possess dynamics that are significantly different from those of synchronous-generator-based sources and as IBR penetrations grow the dynamics of power systems are changing. This article discusses the characteristics of the new dynamics and examines how they can be accommodated into the long-standing categorizations of power system stability in terms of angle, frequency, and voltage stability. It is argued that inverters are causing the frequency range over which angle, frequency, and voltage dynamics act to extend such that the previously partitioned categories are now coupled and further coupled to new electromagnetic modes. While grid-forming (GFM) inverters share many characteristics with generators, grid-following (GFL) inverters are different. This is explored in terms of similarities and differences in synchronization, inertia, and voltage control. The concept of duality is used to unify the synchronization principles of GFM and GFL inverters and, thus, established the generalized angle dynamics. This enables the analytical study of GFM-GFL interaction, which is particularly important to guide the placement of GFM apparatuses and is even more important if GFM inverters are allowed to fall back to the GFL mode during faults to avoid oversizing to support short-term overload. Both GFL and GFM inverters contribute to voltage strength but with marked differences, which implies new features of voltage stability. Several directions for further research are identified, including: 1) extensions of nonlinear stability analysis to accommodate new inverter behaviors with cross-coupled time frames; 2) establishment of spatial–temporal indices of system strength and stability margin to guide the provision of new stability services; and 3) data-driven approaches to combat increased system complexity and confidentiality of inverter models

Delay Measurements and Self Characterisation on FPGAs

This thesis examines new timing measurement methods for self delay characterisation of Field-Programmable Gate Arrays (FPGAs) components and delay measurement of complex circuits on FPGAs. Two novel measurement techniques based on analysis of a circuit's output failure rate and transition probability is proposed for accurate, precise and efficient measurement of propagation delays. The transition probability based method is especially attractive, since it requires no modifications in the circuit-under-test and requires little hardware resources, making it an ideal method for physical delay analysis of FPGA circuits. The relentless advancements in process technology has led to smaller and denser transistors in integrated circuits. While FPGA users benefit from this in terms of increased hardware resources for more complex designs, the actual productivity with FPGA in terms of timing performance (operating frequency, latency and throughput) has lagged behind the potential improvements from the improved technology due to delay variability in FPGA components and the inaccuracy of timing models used in FPGA timing analysis. The ability to measure delay of any arbitrary circuit on FPGA offers many opportunities for on-chip characterisation and physical timing analysis, allowing delay variability to be accurately tracked and variation-aware optimisations to be developed, reducing the productivity gap observed in today's FPGA designs. The measurement techniques are developed into complete self measurement and characterisation platforms in this thesis, demonstrating their practical uses in actual FPGA hardware for cross-chip delay characterisation and accurate delay measurement of both complex combinatorial and sequential circuits, further reinforcing their positions in solving the delay variability problem in FPGAs

Measurement and control of a superconducting quantum processor with a fully integrated radio-frequency system on a chip

We describe a digital microwave platform called Presto, designed for measurement and control of multiple quantum bits (qubits) and based on the third-generation radio-frequency system on a chip. Presto uses direct digital synthesis to create signals up to 9\ua0GHz on 16 synchronous output ports, while synchronously analyzing responses on 16 input ports. Presto has 16 DC-bias outputs, four inputs and four outputs for digital triggers or markers, and two continuous-wave outputs for synthesizing frequencies up to 15\ua0GHz. Scaling to a large number of qubits is enabled through deterministic synchronization of multiple Presto units. A Python application programming interface configures a firmware for synthesis and analysis of pulses, coordinated by an event sequencer. The analysis integrates template matching (matched filtering) and low-latency (184-254\ua0ns) feedback to enable a wide range of multi-qubit experiments. We demonstrate Presto\u27s capabilities with experiments on a sample consisting of two superconducting qubits connected via a flux-tunable coupler. We show single-shot readout and active reset of a single qubit; randomized benchmarking of single-qubit gates showing 99.972% fidelity, limited by the coherence time of the qubit; and calibration of a two-qubit iSWAP gate