A Microfluidic Platform for Precision Small-volume Sample Processing and Its Use to Size Separate Biological Particles with an Acoustic Microdevice.

A major advantage of microfluidic devices is the ability to manipulate small sample volumes, thus reducing reagent waste and preserving precious sample. However, to achieve robust sample manipulation it is necessary to address device integration with the macroscale environment. To realize repeatable, sensitive particle separation with microfluidic devices, this protocol presents a complete automated and integrated microfluidic platform that enables precise processing of 0.15-1.5 ml samples using microfluidic devices. Important aspects of this system include modular device layout and robust fixtures resulting in reliable and flexible world to chip connections, and fully-automated fluid handling which accomplishes closed-loop sample collection, system cleaning and priming steps to ensure repeatable operation. Different microfluidic devices can be used interchangeably with this architecture. Here we incorporate an acoustofluidic device, detail its characterization, performance optimization, and demonstrate its use for size-separation of biological samples. By using real-time feedback during separation experiments, sample collection is optimized to conserve and concentrate sample. Although requiring the integration of multiple pieces of equipment, advantages of this architecture include the ability to process unknown samples with no additional system optimization, ease of device replacement, and precise, robust sample processing

Nanowire Zinc Oxide MOSFET Pressure Sensor

Fabrication and characterization of a new kind of pressure sensor using self-assembly Zinc Oxide (ZnO) nanowires on top of the gate of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is presented. Self-assembly ZnO nanowires were fabricated with a diameter of 80 nm and 800 nm height (80:8 aspect ratio) on top of the gate of the MOSFET. The sensor showed a 110% response in the drain current due to pressure, even with the expected piezoresistive response of the silicon device removed from the measurement. The pressure sensor was fabricated through low temperature bottom up ultrahigh aspect ratio ZnO nanowire growth using anodic alumina oxide (AAO) templates. The pressure sensor has two main components: MOSFET and ZnO nanowires. Silicon Dioxide growth, photolithography, dopant diffusion, and aluminum metallization were used to fabricate a basic MOSFET. In the other hand, a combination of aluminum anodization, alumina barrier layer removal, ZnO atomic layer deposition (ALD), and wet etching for nanowire release were optimized to fabricate the sensor on a silicon wafer. The ZnO nanowire fabrication sequence presented is at low temperature making it compatible with CMOS technology

A High-Performance Triple Patterning Layout Decomposer with Balanced Density

Triple patterning lithography (TPL) has received more and more attentions from industry as one of the leading candidate for 14nm/11nm nodes. In this paper, we propose a high performance layout decomposer for TPL. Density balancing is seamlessly integrated into all key steps in our TPL layout decomposition, including density-balanced semi-definite programming (SDP), density-based mapping, and density-balanced graph simplification. Our new TPL decomposer can obtain high performance even compared to previous state-of-the-art layout decomposers which are not balanced-density aware, e.g., by Yu et al. (ICCAD'11), Fang et al. (DAC'12), and Kuang et al. (DAC'13). Furthermore, the balanced-density version of our decomposer can provide more balanced density which leads to less edge placement error (EPE), while the conflict and stitch numbers are still very comparable to our non-balanced-density baseline

Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically

Layout regularity metric as a fast indicator of process variations

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations

Partial Discharge Mitigation in Power Modules using an Automation-Driven Design Rule Development Method

Power modules used for the conversion and conditioning of electrical power for applications like electric vehicles, more-electric aircraft, the power grid, etc., are largely designed manually by engineers. Design automation of power modules is starting to gain recognition as a timely and necessary alternative to intuitive manual design and fabrication. With increasing need for wide bandgap materials that can operate at higher voltages, and the need to make modules more compact, hazards like electrical breakdown are more likely. Partial discharge (PD) is a silent and invisible precursor to electrical breakdown. It is compounded with compaction, creating a potential for electrical breakdown and catastrophic failure of the module package. Instead of being the limiting factor, or even a hazard, power module packages need to keep pace with the advancements being made in wide bandgap technology. While the automation of power module design is still new, and research and standards on PD in power modules are limited, this dissertation is a significant step in designing for high voltage operation while assessing tradeoffs against module compaction in an electronic design automation tool. This dissertation describes a method of systematically accounting for partial discharge in power modules using a unique approach where improvements to a module layout are determined in terms of design rules. Trace gaps, in this method, are designed to be functions of operating voltage, substrate and encapsulant material choice, and layer thicknesses of the substrate. These design rules are based on simulations that are validated by physical PD experiments. Furthermore, filleting is performed on the final layouts to further reduce PD by reducing the E-field concentrations by a third. This methodology has been implemented in PowerSynth, an in-house hardware-validated electronic design automation tool that performs electro-thermal and mechanical layout optimization. Before the implementation of this work, layouts were agnostic to PD. From the contribution of this work, the layouts now generated by the tool are PD-mitigated, with a maximum operating voltage for each layer stack. Below the rated voltage, the user can choose multiple voltage-trace gap trade off options for the layout. Demonstrating this implementation in this work shows that the user can achieve either a 24% improvement in voltage level, or a 20% improvement in area reduction, or a trade-off combination of the two. As layouts increase in complexity, these improvements will likely grow. The implementation of this work allows room for growth by allowing customized PD data libraries from various manufacturing lines to inform design rules much like a process design kit in the field of integrated circuit design. The designer using PowerSynth can: 1.) Use default libraries for design rules, or 2.) Perform their own simulations to augment the existing PD data library according to the method presented here, or 3.) Fabricate their own test structures and design corresponding simulations to develop their own complete PD data library and import it to PowerSynth. The manufacturable modules resulting from this tool are thus designed to be practical and reliable for high voltage operation

Partial Discharge Mitigation in Power Modules using an Automation-Driven Design Rule Development Method

Power modules used for the conversion and conditioning of electrical power for applications like electric vehicles, more-electric aircraft, the power grid, etc., are largely designed manually by engineers. Design automation of power modules is starting to gain recognition as a timely and necessary alternative to intuitive manual design and fabrication. With increasing need for wide bandgap materials that can operate at higher voltages, and the need to make modules more compact, hazards like electrical breakdown are more likely. Partial discharge (PD) is a silent and invisible precursor to electrical breakdown. It is compounded with compaction, creating a potential for electrical breakdown and catastrophic failure of the module package. Instead of being the limiting factor, or even a hazard, power module packages need to keep pace with the advancements being made in wide bandgap technology. While the automation of power module design is still new, and research and standards on PD in power modules are limited, this dissertation is a significant step in designing for high voltage operation while assessing tradeoffs against module compaction in an electronic design automation tool. This dissertation describes a method of systematically accounting for partial discharge in power modules using a unique approach where improvements to a module layout are determined in terms of design rules. Trace gaps, in this method, are designed to be functions of operating voltage, substrate and encapsulant material choice, and layer thicknesses of the substrate. These design rules are based on simulations that are validated by physical PD experiments. Furthermore, filleting is performed on the final layouts to further reduce PD by reducing the E-field concentrations by a third. This methodology has been implemented in PowerSynth, an in-house hardware-validated electronic design automation tool that performs electro-thermal and mechanical layout optimization. Before the implementation of this work, layouts were agnostic to PD. From the contribution of this work, the layouts now generated by the tool are PD-mitigated, with a maximum operating voltage for each layer stack. Below the rated voltage, the user can choose multiple voltage-trace gap trade off options for the layout. Demonstrating this implementation in this work shows that the user can achieve either a 24% improvement in voltage level, or a 20% improvement in area reduction, or a trade-off combination of the two. As layouts increase in complexity, these improvements will likely grow. The implementation of this work allows room for growth by allowing customized PD data libraries from various manufacturing lines to inform design rules much like a process design kit in the field of integrated circuit design. The designer using PowerSynth can: 1.) Use default libraries for design rules, or 2.) Perform their own simulations to augment the existing PD data library according to the method presented here, or 3.) Fabricate their own test structures and design corresponding simulations to develop their own complete PD data library and import it to PowerSynth. The manufacturable modules resulting from this tool are thus designed to be practical and reliable for high voltage operation

Close-Packed Silicon Microelectrodes for Scalable Spatially Oversampled Neural Recording

Objective: Neural recording electrodes are important tools for understanding neural codes and brain dynamics. Neural electrodes that are closely packed, such as in tetrodes, enable spatial oversampling of neural activity, which facilitates data analysis. Here we present the design and implementation of close-packed silicon microelectrodes to enable spatially oversampled recording of neural activity in a scalable fashion. Methods: Our probes are fabricated in a hybrid lithography process, resulting in a dense array of recording sites connected to submicron dimension wiring. Results: We demonstrate an implementation of a probe comprising 1000 electrode pads, each 9 × 9 μm, at a pitch of 11 μm. We introduce design automation and packaging methods that allow us to readily create a large variety of different designs. Significance: We perform neural recordings with such probes in the live mammalian brain that illustrate the spatial oversampling potential of closely packed electrode sites.Massachusetts Institute of Technology. Simons Center for the Social BrainNational Institutes of Health (U.S.) (NIH Director’s Pioneer Award DP1NS087724)National Institutes of Health (U.S.) (NIH Grant R01NS067199)National Institutes of Health (U.S.) (NIH grant Grant 2R44NS070453- 03A1)National Institutes of Health (U.S.) (NIH Grant R01DA029639)National Science Foundation (U.S.) (Cognitive Rhythms Collaborative, NSF DMS 1042134)Institution of Engineering and Technology (IET) (Harvey Prize)New York Stem Cell FoundationNational Institutes of Health (U.S.) (NIH grant CBET 1053233)United States. Defense Advanced Research Projects Agency (DARPA Grant HR0011-14-2-0004)Paul G. Allen Family Foundatio

Embedding of fibre optic sensors within flexible host

This work deals with the establishment of a UV polymerisation procedure combined with moulding technology towards the development of a mass production technology for the fabrication of flexible polymers with optical fibres embedded. The concept is to provide an artificial sensing skin based on fibre optic sensors which can be applied to irregular or moveable surfaces for distributed pressure applications, as for instance in structural monitoring or rehabilitation. The selected polymers for such an application are here reviewed and their composition adjusted in order to accommodate the required flexibility. As compared to other techniques, UV polymerisation advantages are pointed out when moving towards industrial applications and large scale productions. Meanwhile, curing tests to embed optical fibres in the developed polymers are carried out with an in house developed glass mould set-up and the results are presented. Laser ablation of polymers is also discussed in order to reply the demand of complex fibre layout as for example meandering or curved shape patterns