6,559 research outputs found

    Memory-efficient and fast run-time reconfiguration of regularly structured designs

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    Previous work has shown that run-time reconfiguration of FPGAs benefits greatly from the use of Tunable LUT (TLUT) circuits. These can be rapidly transformed into a specialized LUT circuit and are also very memory efficient when representing regularly structured designs, where the same hardware module is instantiated many times. However, the memory requirements and reconfiguration time of a run-time reconfigurable application are also dependent on the reconfiguration mechanism. In this paper, we will show that the memory requirements of conventional ICAP reconfiguration grow very fast with the number of modules, resulting in excessive memory usage. We propose to use Shift-Register-LUT (SRL) reconfiguration which is faster and results in a memory usage that is independent of the number of modules

    CloudHealth: A Model-Driven Approach to Watch the Health of Cloud Services

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    Cloud systems are complex and large systems where services provided by different operators must coexist and eventually cooperate. In such a complex environment, controlling the health of both the whole environment and the individual services is extremely important to timely and effectively react to misbehaviours, unexpected events, and failures. Although there are solutions to monitor cloud systems at different granularity levels, how to relate the many KPIs that can be collected about the health of the system and how health information can be properly reported to operators are open questions. This paper reports the early results we achieved in the challenge of monitoring the health of cloud systems. In particular we present CloudHealth, a model-based health monitoring approach that can be used by operators to watch specific quality attributes. The CloudHealth Monitoring Model describes how to operationalize high level monitoring goals by dividing them into subgoals, deriving metrics for the subgoals, and using probes to collect the metrics. We use the CloudHealth Monitoring Model to control the probes that must be deployed on the target system, the KPIs that are dynamically collected, and the visualization of the data in dashboards.Comment: 8 pages, 2 figures, 1 tabl

    A dynamically reconfigurable pattern matcher for regular expressions on FPGA

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    In this article we describe how to expand a partially dynamic reconfig- urable pattern matcher for regular expressions presented in previous work by Di- vyasree and Rajashekar [2]. The resulting, extended, pattern matcher is fully dynamically reconfigurable. First, the design is adapted for use with parameterisable configurations, a method for Dynamic Circuit Specialization. Using parameteris- able configurations allows us to achieve the same area gains as the hand crafted reconfigurable design, with the benefit that parameterisable configurations can be applied automatically. This results in a design that is more easily adaptable to spe- cific applications and allows for an easier design exploration. Additionally, the pa- rameterisable configuration implementation is also generated automatically, which greatly reduces the design overhead of using dynamic reconfiguration. Secondly, we propose a number of expansions to the original design to overcome several limitations in the original design that constrain the dynamic reconfigurability of the pattern matcher. We propose two different solutions to dynamically change the character that is matched in a certain block. The resulting pattern matcher, after these changes, is fully dynamically reconfigurable, all aspects of the implemented regular expression can be changed at run-time

    RecoNoC: a reconfigurable network-on-chip

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    This article presents the design of RecoNoC: a compact, highly flexible FPGA-based network-on-chip (NoC), that can be easily adapted for various experiments. In this work, we enhanced this NoC with dynamically reconfigurable shortcuts. These can be used to alter the NoC's topology to adapt to the system's communication needs. The design has been implemented and tested on a Xilinx Virtex-2 Pro FPGA, using the TMAP dynamic datafolding toolflow to automatically generate the reconfigurable hardware and the software reconfiguration procedures. The results show that, using dynamic datafolding, the overhead of introducing this shortcut mechanism is limited

    Self-Healing Partial Reconfiguration of an FPGA

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    The goal of this project, sponsored by General Dynamics, is to create an FPGA-based system capable of detecting and gracefully recovering from errors without compromising system functionality. Previous research developed a prototype for partial reconfiguration, but a major limitation was the need for a PC to partially reprogram the FPGA. By implementing a method of self-reconfiguration and developing a system using triple module redundancy, the FPGA can locate errors and partially self-reconfigure the corrupted areas while maintaining valid system outputs

    Embedded Linux as a Platform for Dynamically Self-Reconfiguring Systems-On-Chip

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    We have previously argued the benefits of embedded Linux as an operating system platform for reconfigurable system-on-chip design. In this paper we describe our approach to building tools for the implementation of dynamically and self-reconfigurable systems, and show that embedded Linux is a natural and powerful platform on which to build these tools. We present examples and demonstrations that show how complex operations such as obtaining partial bit streams from remote servers and initiating reconfiguration are achieved with a single line of Linux shell script

    Department of Computer Science Activity 1998-2004

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    This report summarizes much of the research and teaching activity of the Department of Computer Science at Dartmouth College between late 1998 and late 2004. The material for this report was collected as part of the final report for NSF Institutional Infrastructure award EIA-9802068, which funded equipment and technical staff during that six-year period. This equipment and staff supported essentially all of the department\u27s research activity during that period

    Fast Integration of Hardware Accelerators for Dynamically Reconfigurable Architecture

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    International audienceDynamic reconfiguration of hardware resources is increasingly used in applications as a way to increase performances, resources integration or energy efficiency. As this evolution induces a change of the application execution paradigm, various tools have been set up to develop and manage these applications. But most do not allow direct re-use of legacy code, needing adaptation to match the provided environment. Moreover, partial reconfiguration is only at its early stages, and lacks easy ways of handling. We propose a design methodology and a runtime environment bringing fast integration of legacy hardware accelerators for partial and dynamic reconfigurable hardware architectures. Thanks to it, applications making use of dynamic hardware can be run directly on an Embedded Linux without noticing the reconfiguration flow. Moreover, our design methodology allows providing various implementations of a computation kernel, including both hardware and software ones. The implementation can then be chosen at execution time depending on available resources. In this article, we introduce the generic IP interface description making the re-use process possible. Furthermore, we present the results of a sample application running on our platform using software and hardware implementations. For hardware implementations, we obtain reconfiguration overhead as low as 0.16\% of the total kernel execution time
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