354 research outputs found
Design of Power/Analog/Digital Systems Through Mixed-Level Simulations
In recent years the development of the applications in the field of telecommunications, data processing, control, renewable energy generation, consumer and automotive electronics determined the need for increasingly complex systems, also in shorter time to meet the growing market demand. The increasing complexity is mainly due to the mixed nature of these systems that must be developed to accommodate the new functionalities and to satisfy the more stringent performance requirements of the emerging applications. This means a more complex design and verification process. The key to managing the increased design complexity is a structured and integrated design methodology which allows the sharing of different circuit implementations that can be at transistor level and/or at a higher level (i.e.HDL languages).In order to expedite the mixed systems design process it is necessary to provide: an integrated design methodology; a suitable supporting tool able to manage the entire design process and design complexity and its successive verification.It is essential that the different system blocks (power, analog, digital), described at different level of abstraction, can be co-simulated in the same design context. This capability is referred to as mixed-level simulation.One of the objectives of this research is to design a mixed system application referred to the control of a coupled step-up dc-dc converter. This latter consists of a power stage designed at transistor-level, also including accurate power device models, and the analog controller implemented using VerilogA modules. Digital controllers are becoming very attractive in dc-dc converters for their programmability, ability to implement sophisticated control schemes, and ease of integration with other digital systems. Thus, in this dissertation it will be presented a detailed design of a Flash Analog-to-Digital Converter (ADC). The designed ADC provides medium-high resolution associated to high-speed performance. This makes it useful not only for the control application aforementioned but also for applications with huge requirements in terms of speed and signal bandwidth. The entire design flow of the overall system has been conducted in the Cadence Design Environment that also provides the ability to mixed-level simulations. Furthermore, the technology process used for the ADC design is the IHP BiCMOS 0.25 ”m by using 50 GHz NPN HBT devices
Design and debugging of multi-step analog to digital converters
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling â the short-channel effects â are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-”m CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-”m CMOS process
High linearity analog and mixed-signal integrated circuit design
Linearity is one of the most important specifications in electrical circuits.;In Chapter 1, a ladder-based transconductance networks has been adopted first time to build a low distortion analog filters for low frequency applications. This new technique eliminated the limitation of the application with the traditional passive resistors for low frequency applications. Based on the understanding of this relationship, a strategy for designing high linear analog continuous-time filters has been developed. According to our strategy, a prototype analog integrated filter has been designed and fabricated with AMI05 0.5 um standard CMOS process. Experimental results proved this technique has the ability to provide excellent linearity with very limited active area.;In Chapter 2, the relationships between the transconductance networks and major circuit specifications have been explored. The analysis reveals the trade off between the silicon area saved by the transconductance networks and the some other important specifications such as linearity, noise level and the process variations of the overall circuit. Experimental results of discrete component circuit matched very well with our analytical outcomes to predict the change of linearity and noise performance associated with different transconductance networks.;The Chapter 3 contains the analysis and mathematical proves of the optimum passive area allocations for several most popular analog active filters. Because the total area is now manageable by the technique introduced in the Chapter 1, the further reduce of the total area will be very important and useful for efficient utilizing the silicon area, especially with the today\u27s fast growing area efficiency of the highly density digital circuits. This study presents the mathematical conclusion that the minimum passive area will be achieved with the equalized resistor and capacitor.;In the Chapter 4, a well recognized and highly honored current division circuit has been studied. Although it was claimed to be inherently linear and there are over 60 published works reported with high linearity based on this technique, our study discovered that this current division circuit can achieve, if proper circuit condition being managed, very limited linearity and all the experimental verified performance actually based on more general circuit principle. Besides its limitation, however, we invented a novel current division digital to analog converter (DAC) based on this technique. Benefiting from the simple circuit structure and moderate good linearity, a prototype 8-bit DAC was designed in TSMC018 0.2 um CMOS process and the post layout simulations exhibited the good linearity with very low power consumption and extreme small active area.;As the part of study of the output stage for the current division DAC discussed in the Chapter 4, a current mirror is expected to amplify the output current to drive the low resistive load. The strategy of achieving the optimum bandwidth of the cascode current mirror with fixed total current gain is discussed in the Chapter 5.;Improving the linearity of pipeline ADC has been the hottest and hardest topic in solid-state circuit community for decade. In the Chapter 6, a comprehensive study focus on the existing calibration algorithms for pipeline ADCs is presented. The benefits and limitations of different calibration algorithms have been discussed. Based on the understanding of those reported works, a new model-based calibration is delivered. The simulation results demonstrate that the model-based algorithms are vulnerable to the model accuracy and this weakness is very hard to be removed. From there, we predict the future developments of calibration algorithms that can break the linearity limitations for pipelined ADC. (Abstract shortened by UMI.
Continuous-time low-pass filters for integrated wideband radio receivers
This thesis concentrates on the design and implementation of analog baseband continuous-time low-pass filters for integrated wideband radio receivers. A total of five experimental analog baseband low-pass filter circuits were designed and implemented as a part of five single-chip radio receivers in this work.
After the motivation for the research work presented in this thesis has been introduced, an overview of analog baseband filters in radio receivers is given first. In addition, a review of the three receiver architectures and the three wireless applications that are adopted in the experimental work of this thesis is presented. The relationship between the integrator non-idealities and integrator Q-factor, as well as the effect of the integrator Q-factor on the filter frequency response, are thoroughly studied on the basis of a literature review. The theoretical study that is provided is essential for the gm-C filter synthesis with non-ideal lossy integrators that is presented after the introduction of different techniques to realize integrator-based continuous-time low-pass filters. The filter design approach proposed for gm-C filters is original work and one of the main points in this thesis, in addition to the experimental IC implementations.
Two evolution versions of fourth-order 10-MHz opamp-RC low-pass filters designed and implemented for two multicarrier WCDMA base-station receivers in a 0.25-”m SiGe BiCMOS technology are presented, along with the experimental results of both the low-pass filters and the corresponding radio receivers. The circuit techniques that were used in the three gm-C filter implementations of this work are described and a common-mode induced even-order distortion in a pseudo-differential filter is analyzed. Two evolution versions of fifth-order 240-MHz gm-C low-pass filters that were designed and implemented for two single-chip WiMedia UWB direct-conversion receivers in a standard 0.13-”m and 65-nm CMOS technology, respectively, are presented, along with the experimental results of both the low-pass filters and the second receiver version. The second UWB filter design was also embedded with an ADC into the baseband of a 60-GHz 65-nm CMOS radio receiver. In addition, a third-order 1-GHz gm-C low-pass filter was designed, rather as a test structure, for the same receiver. The experimental results of the receiver and the third gm-C filter implementation are presented
Interface Circuits for Microsensor Integrated Systems
ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.
High-Speed Delta-Sigma Data Converters for Next-Generation Wireless Communication
In recent years, Continuous-time Delta-Sigma(CT-ÎÎŁ) analog-to-digital converters (ADCs) have been extensively investigated for their use in wireless receivers to achieve conversion bandwidths greater than 15 MHz and higher resolution of 10 to 14 bits. This dissertation investigates the current state-of-the-art high-speed single-bit and multi-bit Continuous-time Delta-Sigma modulator (CT-ÎÎŁM) designs and their limitations due to circuit non-idealities in achieving the performance required for next-generation wireless standards. Also, we presented complete architectural and circuit details of a high-speed single-bit and multi-bit CT-ÎÎŁM operating at a sampling rate of 1.25 GSps and 640 MSps respectively (the highest reported sampling rate in a 0.13 ÎŒm CMOS technology node) with measurement results. Further, we propose novel hybrid ÎÎŁ architecture with two-step quantizer to alleviate the bandwidth and resolution bottlenecks associated with the contemporary CT-ÎÎŁM topologies. To facilitate the design with the proposed architecture, a robust systematic design method is introduced to determine the loop-filter coefficients by taking into account the non-ideal integrator response, such as the finite opamp gain and the presence of multiple parasitic poles and zeros. Further, comprehensive system-level simulation is presented to analyze the effect of two-step quantizer non-idealities such as the offset and gain error in the sub-ADCs, and the current mismatch between the MSB and LSB elements in the feedback DAC. The proposed novel architecture is demonstrated by designing a high-speed wideband 4th order CT-ÎÎŁ modulator prototype, employing a two-step quantizer with 5-bits resolution. The proposed modulator takes advantage of the combination of a high-resolution two-step quantization technique and an excess-loop delay (ELD) compensation of more than one clock cycle to achieve lower-power consumption (28 mW), higher dynamic range (\u3e69 dB) with a wide conversion bandwidth (20 MHz), even at a lower sampling rate of 400 MHz. The proposed modulator achieves a Figure of Merit (FoM) of 340 fJ/level
High Performance Integrated Circuit Blocks for High-IF Wideband Receivers
Due to the demand for highâperformance radio frequency (RF) integrated circuit
design in the past years, a systemâonâchip (SoC) that enables integration of analog and
digital parts on the same die has become the trend of the microelectronics industry. As
a result, a major requirement of the next generation of wireless devices is to support
multiple standards in the same chipâset. This would enable a single device to support
multiple peripheral applications and services.
Based on the aforementioned, the traditional superheterodyne frontâend
architecture is not suitable for such applications as it would require a complete receiver
for each standard to be supported. A more attractive alternative is the highintermediate
frequency (IF) radio architecture. In this case the signal is digitalized at an
intermediate frequency such as 200MHz. As a consequence, the baseband operations,
such as downâconversion and channel filtering, become more power and area efficient
in the digital domain. Such architecture releases the specifications for most of the frontâend building blocks, but the linearity and dynamic range of the ADC become the
bottlenecks in this system. The requirements of large bandwidth, high frequency and
enough resolution make such ADC very difficult to realize. Many ADC architectures
were analyzed and ContinuousâTime Bandpass SigmaâDelta (CTâBPâÎŁÎ) architecture was
found to be the most suitable solution in the highâIF receiver architecture since they
combine oversampling and noise shaping to get fairly high resolution in a limited
bandwidth.
A major issue in continuousâtime networks is the lack of accuracy due to powervoltageâ
temperature (PVT) tolerances that lead to over 20% pole variations compared
to their discreteâtime counterparts. An optimally tuned BP ÎŁÎ ADC requires correcting
for center frequency deviations, excess loop delay, and DAC coefficients. Due to these
undesirable effects, a calibration algorithm is necessary to compensate for these
variations in order to achieve high SNR requirements as technology shrinks.
In this work, a novel linearization technique for a Wideband LowâNoise
Amplifier (LNA) targeted for a frequency range of 3â7GHz is presented. Postâlayout
simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm,
respectively. The power consumption of the LNA is 5.8mA from 2V.
Secondly, the design of a CMOS 6th order CT BPâÎŁÎ modulator running at 800
MHz for HighâIF conversion of 10MHz bandwidth signals at 200 MHz is presented. A
novel transconductance amplifier has been developed to achieve high linearity and high
dynamic range at high frequencies. A 2âbit quantizer with offset cancellation is alsopresented. The sixthâorder modulator is implemented using 0.18 um TSMC standard
analog CMOS technology. Postâlayout simulations in cadence demonstrate that the
modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth.
The modulatorâs static power consumption is 107mW from a supply power of ± 0.9V.
Finally, a calibration technique for the optimization of the Noise Transfer
Function CT BP ÎŁÎ modulators is presented. The proposed technique employs two test
tones applied at the input of the quantizer to evaluate the noise transfer function of
the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually
available in mixedâmode systems. Once the ADC output bit stream is captured,
necessary information to generate the control signals to tune the ADC parameters for
best SignalâtoâQuantization Noise Ratio (SQNR) performance is extracted via Leastâ
Mean Squared (LMS) softwareâbased algorithm. Since the two tones are located
outside the band of interest, the proposed global calibration approach can be used
online with no significant effect on the inâband content
System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits
This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand
(UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits.
The MultiBand OFDM (MB-OFDM) proposal for UWB communications has
received significant attention for the implementation of very high data rate (up to
480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion
quadrature mixer, and the overall radio system-level design are proposed for
an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented
in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with
interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in
quadrature with fast hopping, and a linear phase baseband section with 42dB of gain
programmability. The receiver IC mounted on a FR-4 substrate provides a maximum
gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a
2.5V supply.
Two BIT techniques for analog and RF circuits are developed. The goal is to reduce
the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the
magnitude and phase responses at different nodes of an analog circuit. A complete
prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is
demonstrated by performing frequency response measurements in a range of 1 to
130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF
RMS Detector and a methodology for its use in the built-in measurement of the gain and
1dB compression point of RF circuits are proposed to address the problem of on-chip
testing at RF frequencies. The proposed device generates a DC voltage proportional to
the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology
presents and input capacitance <15fF and occupies and area of 0.03mm2. The application
of these two techniques in combination with a loop-back test architecture significantly
enhances the testability of a wireless transceiver system
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