19,268 research outputs found

    Architectures for smart end-user services in the power grid

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    Abstract-The increase of distributed renewable electricity generators, such as solar cells and wind turbines, requires a new energy management system. These distributed generators introduce bidirectional energy flows in the low-voltage power grid, requiring novel coordination mechanisms to balance local supply and demand. Closed solutions exist for energy management on the level of individual homes. However, no service architectures have been defined that allow the growing number of end-users to interact with the other power consumers and generators and to get involved in more rational energy consumption patterns using intuitive applications. We therefore present a common service architecture that allows houses with renewable energy generation and smart energy devices to plug into a distributed energy management system, integrated with the public power grid. Next to the technical details, we focus on the usability aspects of the end-user applications in order to contribute to high service adoption and optimal user involvement. The presented architecture facilitates end-users to reduce net energy consumption, enables power grid providers to better balance supply and demand, and allows new actors to join with new services. We present a novel simulator that allows to evaluate both the power grid and data communication aspects, and illustrate a 22% reduction of the peak load by deploying a central coordinator inside the home gateway of an end-user

    Microprocessor Seminar, phase 2

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    Workshop sessions and papers were devoted to various aspects of microprocessor and large scale integrated circuit technology. Presentations were made on advanced LSI developments for high reliability military and NASA applications. Microprocessor testing techniques were discussed, and test data were presented. High reliability procurement specifications were also discussed

    Conductive inkjet printed antennas on flexible low-cost paper-based substrates for RFID and WSN applications

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    This thesis investigates inkjet-printed flexible antennas fabricated on paper substrates as a system-level solution for ultra-low-cost and mass production of RF structures. These modules are designed for the UHF Radio Frequency Identification (RFID) Tags and Wireless Sensor Nodes (WSN); however the approach could be easily extended to other microwave and wireless applications. Chapter 1 serves as an introduction to RFID technology and its capabilities while listing the major challenges that could potentially hinder RFID practical implementation. Chapter 2 discusses the benefits of using paper as a substrate for high-frequency applications, reporting its very good electrical/dielectric performance up to at least 1 GHz. The dielectric properties are studied by using the microstrip ring resonator. Brief discussion on Liquid Crystal Polymer (LCP) is also given in this chapter. Chapter 3 gives details about the inkjet printing technology, including the characterization of the conductive ink, which consists of nano-silver-particles, while highlighting the importance of this technology as a fast and simple fabrication technique especially on flexible organic (e.g.LCP) or paper-based substrates. Chapter 4 focuses on antenna designs. Four examples are given to provide: i) matching techniques to complex IC impedance, ii) proof of concept of inkjet printing on paper substrate through measurement results, iii) demonstration of a fully-integrated wireless sensor modules on paper and show a 2D sensor integration with an RFID tag module on paper. Chapter 5 concludes the thesis by explaining the importance of this work in creating a first step towards an environmentally friendly generation of "green" RF electronics and modules.M.S.Committee Chair: Dr. Manos Tentzeris; Committee Member: Dr. Gregory Durgin; Committee Member: Dr. Joy Laska

    REAM intensity modulator-enabled 10Gb/s colorless upstream transmission of real-time optical OFDM signals in a single-fiber-based bidirectional PON architecture

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    Reflective electro-absorption modulation-intensity modulators (REAM-IMs) are utilized, for the first time, to experimentally demonstrate colorless ONUs in single-fiber-based, bidirectional, intensity-modulation and direct-detection (IMDD), optical OFDM PONs (OOFDM-PONs) incorporating 25km SSMFs and OLT-side-seeded CW optical signals. The colorlessness of the REAM-IMs is characterized, based on which optimum REAM-IM operating conditions are identified. In the aforementioned PON architecture, 10Gb/s colorless upstream transmissions of end-to-end realtime OOFDM signals are successfully achieved for various wavelengths within the entire C-band. Over such a wavelength window, corresponding minimum received optical powers at the FEC limit vary in a range as small as <0.5dB. In addition, experimental measurements also indicate that Rayleigh backscattering imposes a 2.8dB optical power penalty on the 10Gb/s over 25km upstream OOFDM signal transmission. Furthermore, making use of on-line adaptive bit and power loading, a linear trade-off between aggregated signal line rate and optical power budget is observed, which shows that, for the present PON system, a 10% reduction in signal line rate can improve the optical power budget by 2.6dB. © 2012 Optical Society of America

    Infrastructure for Detector Research and Development towards the International Linear Collider

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    The EUDET-project was launched to create an infrastructure for developing and testing new and advanced detector technologies to be used at a future linear collider. The aim was to make possible experimentation and analysis of data for institutes, which otherwise could not be realized due to lack of resources. The infrastructure comprised an analysis and software network, and instrumentation infrastructures for tracking detectors as well as for calorimetry.Comment: 54 pages, 48 picture

    Innovative Techniques for Testing and Diagnosing SoCs

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    We rely upon the continued functioning of many electronic devices for our everyday welfare, usually embedding integrated circuits that are becoming even cheaper and smaller with improved features. Nowadays, microelectronics can integrate a working computer with CPU, memories, and even GPUs on a single die, namely System-On-Chip (SoC). SoCs are also employed on automotive safety-critical applications, but need to be tested thoroughly to comply with reliability standards, in particular the ISO26262 functional safety for road vehicles. The goal of this PhD. thesis is to improve SoC reliability by proposing innovative techniques for testing and diagnosing its internal modules: CPUs, memories, peripherals, and GPUs. The proposed approaches in the sequence appearing in this thesis are described as follows: 1. Embedded Memory Diagnosis: Memories are dense and complex circuits which are susceptible to design and manufacturing errors. Hence, it is important to understand the fault occurrence in the memory array. In practice, the logical and physical array representation differs due to an optimized design which adds enhancements to the device, namely scrambling. This part proposes an accurate memory diagnosis by showing the efforts of a software tool able to analyze test results, unscramble the memory array, map failing syndromes to cell locations, elaborate cumulative analysis, and elaborate a final fault model hypothesis. Several SRAM memory failing syndromes were analyzed as case studies gathered on an industrial automotive 32-bit SoC developed by STMicroelectronics. The tool displayed defects virtually, and results were confirmed by real photos taken from a microscope. 2. Functional Test Pattern Generation: The key for a successful test is the pattern applied to the device. They can be structural or functional; the former usually benefits from embedded test modules targeting manufacturing errors and is only effective before shipping the component to the client. The latter, on the other hand, can be applied during mission minimally impacting on performance but is penalized due to high generation time. However, functional test patterns may benefit for having different goals in functional mission mode. Part III of this PhD thesis proposes three different functional test pattern generation methods for CPU cores embedded in SoCs, targeting different test purposes, described as follows: a. Functional Stress Patterns: Are suitable for optimizing functional stress during I Operational-life Tests and Burn-in Screening for an optimal device reliability characterization b. Functional Power Hungry Patterns: Are suitable for determining functional peak power for strictly limiting the power of structural patterns during manufacturing tests, thus reducing premature device over-kill while delivering high test coverage c. Software-Based Self-Test Patterns: Combines the potentiality of structural patterns with functional ones, allowing its execution periodically during mission. In addition, an external hardware communicating with a devised SBST was proposed. It helps increasing in 3% the fault coverage by testing critical Hardly Functionally Testable Faults not covered by conventional SBST patterns. An automatic functional test pattern generation exploiting an evolutionary algorithm maximizing metrics related to stress, power, and fault coverage was employed in the above-mentioned approaches to quickly generate the desired patterns. The approaches were evaluated on two industrial cases developed by STMicroelectronics; 8051-based and a 32-bit Power Architecture SoCs. Results show that generation time was reduced upto 75% in comparison to older methodologies while increasing significantly the desired metrics. 3. Fault Injection in GPGPU: Fault injection mechanisms in semiconductor devices are suitable for generating structural patterns, testing and activating mitigation techniques, and validating robust hardware and software applications. GPGPUs are known for fast parallel computation used in high performance computing and advanced driver assistance where reliability is the key point. Moreover, GPGPU manufacturers do not provide design description code due to content secrecy. Therefore, commercial fault injectors using the GPGPU model is unfeasible, making radiation tests the only resource available, but are costly. In the last part of this thesis, we propose a software implemented fault injector able to inject bit-flip in memory elements of a real GPGPU. It exploits a software debugger tool and combines the C-CUDA grammar to wisely determine fault spots and apply bit-flip operations in program variables. The goal is to validate robust parallel algorithms by studying fault propagation or activating redundancy mechanisms they possibly embed. The effectiveness of the tool was evaluated on two robust applications: redundant parallel matrix multiplication and floating point Fast Fourier Transform

    Solar thermal power systems point-focusing thermal and electric applications projects. Volume 1: Executive summary

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    The activities of the Point-Focusing Thermal and Electric Applications (PETEA) project for the fiscal year 1979 are summarized. The main thrust of the PFTEA Project, the small community solar thermal power experiment, was completed. Concept definition studies included a small central receiver approach, a point-focusing distributed receiver system with central power generation, and a point-focusing distributed receiver concept with distributed power generation. The first experiment in the Isolated Application Series was initiated. Planning for the third engineering experiment series, which addresses the industrial market sector, was also initiated. In addition to the experiment-related activities, several contracts to industry were let and studies were conducted to explore the market potential for point-focusing distributed receiver (PFDR) systems. System analysis studies were completed that looked at PFDR technology relative to other small power system technology candidates for the utility market sector
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