Analog Property Checkers: A Ddr2 Case Study

The formal specification component of verification can be exported to simulation through the idea of property checkers. The essence of this approach is the automatic construction of an observer from the specification in the form of a program that can be interfaced with a simulator and alert the user if the property is violated by a simulation trace. Although not complete, this lighter approach to formal verification has been effectively used in software and digital hardware to detect errors. Recently, the idea of property checkers has been extended to analog and mixed-signal systems. In this paper, we apply the property-based checking methodology to an industrial and realistic example of a DDR2 memory interface. The properties describing the DDR2 analog behavior are expressed in the formal specification language stl/psl in form of assertions. The simulation traces generated from an actual DDR2 interface design are checked with respect to the stl/psl assertions using the amt tool. The focus of this paper is on the translation of the official (informal and descriptive) specification of two non-trivial DDR2 properties into stl/psl assertions. We study both the benefits and the current limits of such approach

Analog property checkers: a DDR2 case study

The formal specification component of verification can be exported to simulation through the idea of property checkers. The essence of this approach is the automatic construction of an observer from the specification in the form of a program that can be interfaced with a simulator and alert the user if the property is violated by a simulation trace. Although not complete, this lighter approach to formal verification has been effectively used in software and digital hardware to detect errors. Recently, the idea of property checkers has been extended to analog and mixed-signal systems. In this paper, we apply the property-based checking methodology to an industrial and realistic example of a DDR2 memory interface. The properties describing the DDR2 analog behavior are expressed in the formal specification language stl/psl in form of assertions. The simulation traces generated from an actual DDR2 interface design are checked with respect to the stl/psl assertions using the amt tool. The focus of this paper is on the translation of the official (informal and descriptive) specification of two non-trivial DDR2 properties into stl/psl assertions. We study both the benefits and the current limits of such approac

CDC logic verification in RTL design

Abstract. This bachelor’s thesis provides overview of the clock domain crossing verification in RTL design. Metastability problem and different synchronization methods are explained, and the CDC verification flow is introduced. The work is focused to discuss about different challenges in the CDC verification.CDC Logic Verification in RTL Design CDC logiikan tarkastaminen RTL suunnittellussa. Tiivistelmä. Tämä kandidaatintyö antaa yleiskatsauksen kelloalueylitysten verifiointiin RTL suunnittelussa. Metastabiilisuus ja erilaiset synkronointitavat selitetään sekä CDC verifiointiprosessi esitetään. Työ painottuu tarkastelemaan erilaisia haasteita CDC verifioinnissa

Towards the Formal Verification of a Distributed Real-Time Automotive System

We present the status of a project which aims at building, formally and pervasively verifying a distributed automotive system. The target system is a gate-level model which consists of several interconnected electronic control units with independent clocks. This model is verified against the specification as seen by a system programmer. The automotive system is implemented on several FPGA boards. The pervasive verification is carried out using combination of interactive theorem proving (Isabelle/HOL) and model checking (LTL)

Store-and-forward CDC packet transmission in digital systems

Data transmission across clock domains is a major point of interest by ASIC designers as a limited bandwidth can be responsible for a processing power bottleneck that affects the entire system. Clock domain crossing is inherently expensive in terms of area and latency as it requires overcoming issues related to the physical nature of integrated circuit latches, in particular metastability. These issues are dangerous as they do not manifest in RTL simulation. Due to this, designers often opt for generic data synchronisation solutions that are not fully suited to the nature of the data being transferred.This dissertation presents a clock domain crossing mechanism that allows two clock domains to share a common memory to transfer packet-based data. The mechanism consists in a memory controller that coordinates commands from a push (write) domain and a pop (read) domain.The main objective of the memory controller project consists in the implementation of efficient synchronisation methods in order to eliminate the need for separate synchronisation and storage memories. In essence, the controller is an extension of an asynchronous FIFO controller with added functionality, supporting multiple virtual FIFOs and variable length data packets

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Multi-Write distributor bus

Abstract. This thesis studies the design and verification for Multi-Write distribution with AMBA AXI protocol to reduce the SW execution time. First, Bus protocol and microarchitecture is looked at and Verilog/VHDL coding processes are studied. And appropriate verification method is examined. Last challenges/open items and possibilities for the future improvements are discussed. The development of standalone design/verification environment build is covered in the work. Moni-kirjoitus jakeluväylä. Tiivistelmä. Tässä opinnäytetyössä tutkitaan monikirjoitusjakelijan suunnittelua ja verifiointia AMBA AXI protokollalla ohjelmiston suoritusajan lyhentämiseksi. Ensin tarkastellaan väyläprotokollaa ja mikroarkkitehtuuria ja tutkitaan Verilog/VHDL koodausprosesseja sekä asianmukaisia verifikaatio menetelmiä. Viimeiseksi keskustellaan haasteista/avoimista kohteista ja mahdollisista tulevaisuuden parannuksista. Työssä käsitellään erillisen suunnittelu-/todentamisympäristön rakentamisen kehittämistä