A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Fault simulation for structural testing of analogue integrated circuits

In this thesis the ANTICS analogue fault simulation software is described which provides a statistical approach to fault simulation for accurate analogue IC test evaluation. The traditional figure of fault coverage is replaced by the average probability of fault detection. This is later refined by considering the probability of fault occurrence to generate a more realistic, weighted test metric. Two techniques to reduce the fault simulation time are described, both of which show large reductions in simulation time with little loss of accuracy. The final section of the thesis presents an accurate comparison of three test techniques and an evaluation of dynamic supply current monitoring. An increase in fault detection for dynamic supply current monitoring is obtained by removing the DC component of the supply current prior to measurement

Moving Towards Analog Functional Safety

Over the past century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power systems. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The standard ISO 26262 related to functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardizing fault modeling, injection and simulation mainly focused on digital circuits and disregarding analog ones. An initial attempt is being made with the IEEE P2427 standard draft standard that started to give this field a structured and formal organization. In this context, new fault models, injection, and abstraction methodologies for analog circuits are proposed in this thesis to enhance this application field. The faults proposed by the IEEE P2427 standard draft standard are initially evaluated to understand the associated fault behaviors during the simulation. Moreover, a novel approach is presented for modeling realistic stuck-on/off defects based on oxide defects. These new defects proposed are required because digital stuck-at-fault models where a transistor is frozen in on-state or offstate may not apply well on analog circuits because even a slight variation could create deviations of several magnitudes. Then, for validating the proposed defects models, a novel predictive fault grouping based on faulty AC matrices is applied to group faults with equivalent behaviors. The proposed fault grouping method is computationally cheap because it avoids performing DC or transient simulations with faults injected and limits itself to faulty AC simulations. Using AC simulations results in two different methods that allow grouping faults with the same frequency response are presented. The first method is an AC-based grouping method that exploits the potentialities of the S-parameters ports. While the second is a Circle-based grouping based on the circle-fitting method applied to the extracted AC matrices. Finally, an open-source framework is presented for the fault injection and manipulation perspective. This framework relies on the shared semantics for reading, writing, or manipulating transistor-level designs. The ultimate goal of the framework is: reading an input design written in a specific syntax and then allowing to write the same design in another syntax. As a use case for the proposed framework, a process of analog fault injection is discussed. This activity requires adding, removing, or replacing nodes, components, or even entire sub-circuits. The framework is entirely written in C++, and its APIs are also interfaced with Python. The entire framework is open-source and available on GitHub. The last part of the thesis presents abstraction methodologies that can abstract transistor level models into Verilog-AMS models and Verilog- AMS piecewise and nonlinear models into C++. These abstracted models can be integrated into heterogeneous systems. The purpose of integration is the simulation of heterogeneous components embedded in a Virtual Platforms (VP) needs to be fast and accurate

Symbolic tolerance and sensitivity analysis of large scale electronic circuits

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Automated simulation of faults in analog circuits based on parallel paradigm

© 2017 IEEE. Fault simulation is very important task for testing and fault diagnostics based on the concept of simulation before test. Catastrophic and parametric faults as well as component tolerances can make strong or weak influence on a correct circuit behavior. Therefore it is necessary to estimate such influence during design stage in order to provide high quality testing and diagnosis for the circuit under test. The number of potential faults in analog circuits is tremendous and the fault simulation requires essential computational resources as well as takes much time. The approach to the fault simulation in analog circuits based on parallel paradigm providing automation of the design-for-testability concept and essential reduction of the fault simulation time is proposed. The decomposition of the fault simulation task according to parallel paradigm is presented. The architecture of parallel simulation system is considered, and FSM for operation of the main host and executive nodes are described. Two scenarios of possible interoperability between the main host and executive nodes based on cascade scheme and deferred scheme are proposed. Experimental results for both scenarios are presented

Defect-based testing of LTS digital circuits

A Defect-Based Test (DBT) methodology for Superconductor Electronics (SCE) is presented in this thesis, so that commercial production and efficient testing of systems can be implemented in this technology in the future. In the first chapter, the features and prospects for SCE have been presented. The motivation for this research and the outline of the thesis were also described in Chapter 1. It has been shown that high-end applications such as Software-Defined Radio (SDR) and petaflop computers which are extremely difficult to implement in top-of-the-art semiconductor technologies can be realised using SCE. But, a systematic structural test methodology had yet to be developed for SCE and has been addressed in this thesis. A detailed introduction to Rapid Single-Flux Quantum (RSFQ) circuits was presented in Chapter 2. A Josephson Junction (JJ) was described with associated theory behind its operation. The JJ model used in the simulator used in this research work was also presented. RSFQ logic with logic protocols as well as the design and implementation of an example D-type flip-flop (DFF) was also introduced. Finally, advantages and disadvantages of RSFQ circuits have been discussed with focus on the latest developments in the field. Various techniques for testing RSFQ circuits were discussed in Chapter 3. A Process Defect Monitor (PDM) approach was presented for fabrication process analysis. The presented defect-monitor structures were used to gather measurement data, to find the probability of the occurrence of defects in the process which forms the first step for Inductive Fault Analysis (IFA). Results from measurements on these structures were used to create a database for defects. This information can be used as input for performing IFA. "Defect-sprinkling" over a fault-free circuit can be carried out according to the measured defect densities over various layers. After layout extraction and extensive fault simulation, the resulting information will indicate realistic faults. In addition, possible Design-for-Testability (DfT) schemes for monitoring Single-Flux Quantum (SFQ) pulses within an RSFQ circuit has also been discussed in Chapter 3. The requirement for a DfT scheme is inevitable for RSFQ circuits because of their very high frequency of operation and very low operating temperature. It was demonstrated how SFQ pulses can be monitored at an internal node of an SCE circuit, introducing observability using Test-Point Insertion (TPI). Various techniques were discussed for the introduction of DfT and to avoid the delay introduced by the DfT structure if it is required. The available features in the proposed design for customising the detector make it attractive for a detailed DBT of RSFQ circuits. The control of internal nodes has also been illustrated using TPI. The test structures that were designed and implemented to determine the occurrence of defects in the processes can also be used to locate the position for the insertion of the above mentioned DfT structures

OSCILLATION-BASED TESTING METHOD FOR DETECTING SWITCH FAULTS IN HIGH-Q SC BIQUAD FILTERS

Testing switched capacitor circuits is a challenge due to the diversity of the possible faults. A special problem encountered is the synthesis of the test signal that will control and will make the fault-effect observable at the test point. The oscillation based method which was adopted for testing in these proceedings resolves that important issue by his nature. Here we discuss the properties of the method and the conditions to be fulfilled in order to implement it in the right way. To achieve that we resolved the problem of synthesis of the positive feed-back circuit and the choice of a proper model of the operational amplifier. In that way a realistic foundation to the testing process was generated. A second order notch cell was chosen as a case-study. Fault dictionaries were developed related to the catastrophic faults of the switches used within the cell. The results reported here are a continuation of our previous work and are complimentary to some other already published

Investigation into voltage and process variation-aware manufacturing test

Increasing integration and complexity in IC design provides challenges for manufacturing testing. This thesis studies how process and supply voltage variation influence defect behaviour to determine the impact on manufacturing test cost and quality. The focus is on logic testing of static CMOS designs with respect to two important defect types in deep submicron CMOS: resistive bridges and full opens. The first part of the thesis addresses testing for resistive bridge defects in designs with multiple supply voltage settings. To enable analysis, a fault simulator is developed using a supply voltage-aware model for bridge defect behaviour. The analysis shows that for high defect coverage it is necessary to perform test for more than one supply voltage setting, due to supply voltage-dependent behaviour. A low-cost and effective test method is presented consisting of multi-voltage test generation that achieves high defect coverage and test set size reduction without compromise to defect coverage. Experiments on synthesised benchmarks with realistic bridge locations validate the proposed method.The second part focuses on the behaviour of full open defects under supply voltage variation. The aim is to determine the appropriate value of supply voltage to use when testing. Two models are considered for the behaviour of full open defects with and without gate tunnelling leakage influence. Analysis of the supply voltage-dependent behaviour of full open defects is performed to determine if it is required to test using more than one supply voltage to detect all full open defects. Experiments on synthesised benchmarks using an extended version of the fault simulator tool mentioned above, measure the quantitative impact of supply voltage variation on defect coverage.The final part studies the impact of process variation on the behaviour of bridge defects. Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation

Fault-based Analysis of Industrial Cyber-Physical Systems

The fourth industrial revolution called Industry 4.0 tries to bridge the gap between traditional Electronic Design Automation (EDA) technologies and the necessity of innovating in many indus- trial fields, e.g., automotive, avionic, and manufacturing. This complex digitalization process in- volves every industrial facility and comprises the transformation of methodologies, techniques, and tools to improve the efficiency of every industrial process. The enhancement of functional safety in Industry 4.0 applications needs to exploit the studies related to model-based and data-driven anal- yses of the deployed Industrial Cyber-Physical System (ICPS). Modeling an ICPS is possible at different abstraction levels, relying on the physical details included in the model and necessary to describe specific system behaviors. However, it is extremely complicated because an ICPS is com- posed of heterogeneous components related to different physical domains, e.g., digital, electrical, and mechanical. In addition, it is also necessary to consider not only nominal behaviors but even faulty behaviors to perform more specific analyses, e.g., predictive maintenance of specific assets. Nevertheless, these faulty data are usually not present or not available directly from the industrial machinery. To overcome these limitations, constructing a virtual model of an ICPS extended with different classes of faults enables the characterization of faulty behaviors of the system influenced by different faults. In literature, these topics are addressed with non-uniformly approaches and with the absence of standardized and automatic methodologies for describing and simulating faults in the different domains composing an ICPS. This thesis attempts to overcome these state-of-the-art gaps by proposing novel methodologies, techniques, and tools to: model and simulate analog and multi-domain systems; abstract low-level models to higher-level behavioral models; and monitor industrial systems based on the Industrial Internet of Things (IIOT) paradigm. Specifically, the proposed contributions involve the exten- sion of state-of-the-art fault injection practices to improve the ICPSs safety, the development of frameworks for safety operations automatization, and the definition of a monitoring framework for ICPSs. Overall, fault injection in analog and digital models is the state of the practice to en- sure functional safety, as mentioned in the ISO 26262 standard specific for the automotive field. Starting from state-of-the-art defects defined for analog descriptions, new defects are proposed to enhance the IEEE P2427 draft standard for analog defect modeling and coverage. Moreover, dif- ferent techniques to abstract a transistor-level model to a behavioral model are proposed to speed up the simulation of faulty circuits. Therefore, unlike the electrical domain, there is no extensive use of fault injection techniques in the mechanical one. Thus, extending the fault injection to the mechanical and thermal fields allows for supporting the definition and evaluation of more reliable safety mechanisms. Hence, a taxonomy of mechanical faults is derived from the electrical domain by exploiting the physical analogies. Furthermore, specific tools are built for automatically instru- menting different descriptions with multi-domain faults. The entire work is proposed as a basis for supporting the creation of increasingly resilient and secure ICPS that need to preserve functional safety in any operating context