ASIC Technology Migrations: A Design Guide for First Pass Success

This thesis presents a study of Application Specific Integrated Circuit (ASIC) technology migrations. An overview of the design flow methodology used for completing a ASIC design from concept to silicon is presented. The design flow is then augmented with special considerations specifically for ASIC technology migrations. An ASIC technology migration design example, using the special considerations, is preseted. Finally, a summary is presented with considerations regarding future work

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

Power constrained test scheduling in system-on-chip design

With the development of VLSI technologies, especially with the coming of deep sub-micron semiconductor process technologies, power dissipation becomes a critical factor that cannot be ignored either in normal operation or in test mode of digital systems. Test scheduling has to take into consideration of both test concurrency and power dissipation constraints. For satisfying high fault coverage goals with minimum test application time under certain power dissipation constraints, the testing of all components on the system should be performed in parallel as much as possible. The main objective of this thesis is to address the test-scheduling problem faced by SOC designers at system level. Through the analysis of several existing scheduling approaches, we enlarge the basis that current approaches based on to minimize test application time and propose an efficient and integrated technique for the test scheduling of SOCs under power-constraint. The proposed merging approach is based on a tree growing technique and can be used to overlay the block-test sessions in order to reduce further test application time. A number of experiments, based on academic benchmarks and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed approaches

seihin kaihatsu ni okeru sekkei fuka to sono teigen : sekkei purosesu no koritsuka to kaizen ni kansuru kenkyu

制度:新 ; 文部省報告番号:甲2267号 ; 学位の種類:博士(学術) ; 授与年月日:2006/9/15 ; 早大学位記番号:新429

Improving rewiring scheme and its applications on various circuit design problems.

Lo Wing Hang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 60-61).Abstracts in English and Chinese.Abstract --- p.iChapter 1 --- Introduction --- p.1Chapter 2 --- Preliminaries --- p.5Chapter 2.1 --- Backgrounds and Definitions --- p.5Chapter 2.1.1 --- Boolean Network --- p.5Chapter 2.1.2 --- Transitive Fanin and Fanout Cone --- p.6Chapter 2.1.3 --- Controlling and Sensitizing Values --- p.6Chapter 2.1.4 --- Stuck-at Faults and Test Generation --- p.6Chapter 2.1.5 --- Mandatory Assignments --- p.8Chapter 2.2 --- Review of ATPG-based Rewiring --- p.9Chapter 3 --- Improved Single-Pass Rewiring Scheme Using Inconsistent Assignments --- p.14Chapter 3.1 --- Introduction --- p.14Chapter 3.2 --- Overview of FIRE --- p.15Chapter 3.3 --- Alternative Wire Identification Method --- p.17Chapter 3.3.1 --- Identifying Candidate Wires --- p.17Chapter 3.3.2 --- Redundancy Test on Candidate Wire --- p.18Chapter 3.4 --- Redundancy Identification Using Inconsistent Assignments --- p.21Chapter 3.5 --- Experimental Results --- p.26Chapter 3.6 --- Conclusions --- p.28Chapter 4 --- Improving Circuit Partitioning With Rewiring Techniques --- p.29Chapter 4.1 --- Introduction --- p.29Chapter 4.2 --- Implementation of Rewiring Schemes --- p.31Chapter 4.3 --- Coupling Partitioning Algorithm With Rewiring Techniques --- p.33Chapter 4.4 --- Experimental Results --- p.37Chapter 4.5 --- Conclusions --- p.43Chapter 5 --- Circuit Logic Level Reduction by Rewiring for FPGA Mapping --- p.45Chapter 5.1 --- Introduction --- p.45Chapter 5.2 --- Overview of the Technology Mapping Problem --- p.47Chapter 5.2.1 --- Problem Formulation --- p.47Chapter 5.2.2 --- FlowMap Algorithm Outline --- p.49Chapter 5.3 --- Logic Level Reduction by Rewiring Transformations --- p.51Chapter 5.4 --- Experimental Results --- p.54Chapter 5.5 --- Conclusions --- p.57Chapter 6 --- Conclusions and Future Works --- p.58Bibliography --- p.6

Design of 2D discrete cosine transform using CORDIC architectures in VHDL

The Discrete Cosine Transform is one of the most widely transform techniques in digital signal processing. In addition, this is also most computationally intensive transforms which require many multiplications and additions. Real time data processing necessitates the use of special purpose hardware which involves hardware efficiency as well as high throughput. Many DCT algorithms were proposed in order to achieve high speed DCT. Those architectures which involves multipliers, for example Chen’s algorithm has less regular architecture due to complex routing and requires large silicon area. On the other hand, the DCT architecture based on distributed arithmetic (DA) which is also a multiplier less architecture has the inherent disadvantage of less throughputs because of the ROM access time and the need of accumulator. Also this DA algorithm requires large silicon area if it requires large ROM size. Systolic array architecture for the real-time DCT computation may have the large number of gates and clock skew problem. The other ways of implementation of DCT which involves in multiplierless, thus power efficient and which results in regular architecture and less complicated routing, consequently less area, simultaneously lead to high throughput. So for that purpose CORDIC seems to be a best solution. CORDIC offers a unified iterative formulation to efficiently evaluate the rotation operation. This thesis presents the implementation of 2D Discrete Cosine Transform (DCT) using the Angle Recoded (AR) Cordic algorithm, the new scaling less CORDIC algorithm and the conventional Chen’s algorithm which is multiplier dependant algorithm. The 2D DCT is implemented by exploiting the Separability property of 2D Discrete Cosine Transform. Here first one dimensional DCT is designed first and later a transpose buffer which consists of 64 memory elements, fully pipelined is designed. Later all these blocks are joined with the help of a controller element which is a mealy type FSM which produces some status signals also. The three resulting architectures are all well synthesized in Xilinx 9.1ise, simulated in Modelsim 5.6f and the power is calculated in Xilinx Xpower. Results prove that AR Cordic algorithm is better than Chen’s algorithm, even the new scaling less CORDIC algorithm

Embedded System Design

A unique feature of this open access textbook is to provide a comprehensive introduction to the fundamental knowledge in embedded systems, with applications in cyber-physical systems and the Internet of things. It starts with an introduction to the field and a survey of specification models and languages for embedded and cyber-physical systems. It provides a brief overview of hardware devices used for such systems and presents the essentials of system software for embedded systems, including real-time operating systems. The author also discusses evaluation and validation techniques for embedded systems and provides an overview of techniques for mapping applications to execution platforms, including multi-core platforms. Embedded systems have to operate under tight constraints and, hence, the book also contains a selected set of optimization techniques, including software optimization techniques. The book closes with a brief survey on testing. This fourth edition has been updated and revised to reflect new trends and technologies, such as the importance of cyber-physical systems (CPS) and the Internet of things (IoT), the evolution of single-core processors to multi-core processors, and the increased importance of energy efficiency and thermal issues