37 research outputs found

    Network-on-Chip

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    Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

    Mobile Ad-Hoc Networks

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    Being infrastructure-less and without central administration control, wireless ad-hoc networking is playing a more and more important role in extending the coverage of traditional wireless infrastructure (cellular networks, wireless LAN, etc). This book includes state-of the-art techniques and solutions for wireless ad-hoc networks. It focuses on the following topics in ad-hoc networks: vehicular ad-hoc networks, security and caching, TCP in ad-hoc networks and emerging applications. It is targeted to provide network engineers and researchers with design guidelines for large scale wireless ad hoc networks

    On the Secure and Resilient Design of Connected Vehicles: Methods and Guidelines

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    Vehicles have come a long way from being purely mechanical systems to systems that consist of an internal network of more than 100 microcontrollers and systems that communicate with external entities, such as other vehicles, road infrastructure, the manufacturer’s cloud and external applications. This combination of resource constraints, safety-criticality, large attack surface and the fact that millions of people own and use them each day, makes securing vehicles particularly challenging as security practices and methods need to be tailored to meet these requirements.This thesis investigates how security demands should be structured to ease discussions and collaboration between the involved parties and how requirements engineering can be accelerated by introducing generic security requirements. Practitioners are also assisted in choosing appropriate techniques for securing vehicles by identifying and categorising security and resilience techniques suitable for automotive systems. Furthermore, three specific mechanisms for securing automotive systems and providing resilience are designed and evaluated. The first part focuses on cyber security requirements and the identification of suitable techniques based on three different approaches, namely (i) providing a mapping to security levels based on a review of existing security standards and recommendations; (ii) proposing a taxonomy for resilience techniques based on a literature review; and (iii) combining security and resilience techniques to protect automotive assets that have been subject to attacks. The second part presents the design and evaluation of three techniques. First, an extension for an existing freshness mechanism to protect the in-vehicle communication against replay attacks is presented and evaluated. Second, a trust model for Vehicle-to-Vehicle communication is developed with respect to cyber resilience to allow a vehicle to include trust in neighbouring vehicles in its decision-making processes. Third, a framework is presented that enables vehicle manufacturers to protect their fleet by detecting anomalies and security attacks using vehicle trust and the available data in the cloud

    Cross-layer fault tolerance in networks-on-chip

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    The design of Networks-on-Chip follows the Open Systems Interconnection (OSI) reference model. The OSI model defines strictly separated network abstraction layers and specifies their functionality. Each layer has layer-specific information about the network that can be exclusively accessed by the methods of the layer. Adhering to the strict layer boundaries, however, leads to methods of the individual layers working in isolation from each other. This lack of interaction between methods is disadvantageous for fault diagnosis and fault tolerance in Networks-on-Chip as it results in solutions that have a high effort in terms of the time and implementation costs required to deal with faults. For Networks-on-Chip cross-layer design is considered as a promising method to remedy these shortcomings. It removes the strict layer boundaries by the exchange of information between layers. This interaction enables methods of different layers to cooperate, and thus, deal with faults more efficiently. Furthermore, providing lower layer information to the software allows hardware methods to be implemented as software tasks resulting in a reduction of the hardware complexity. The goal of this dissertation is the investigation of cross-layer design for fault diagnosis and fault tolerance in Networks-on-Chip. For fault diagnosis a scheme is proposed that allows the interaction of protocol-based diagnosis of the transport layer with functional diagnosis of the network layer and structural diagnosis of the physical layer by exchanging diagnostic information. The techniques use this information for optimizing their own diagnosis process. For protocol-based diagnosis on the transport layer, a diagnosis protocol is proposed that is able to locate faulty links, switches, and crossbar connections. For this purpose, the technique utilizes available information of lower layers. As proof of concept for the proposed interaction scheme, the diagnosis protocol is combined with a functional and a structural diagnosis approach and the performance and diagnosis quality of the resulting combinations is investigated. The results show that the combinations of the diagnosis protocol with one of the lower layer techniques have a considerably reduced fault localization latency compared to the functional and the structural standalone techniques. This reduction, however, comes at the expense of a reduced diagnosis quality. In terms of fault tolerance, the focus of this dissertation is on the design and implementation of cross-layer approaches utilizing software methods to provide fault tolerance for network layer routings. Two approaches for different routings are presented. The requirements to provide information of lower layers to the software using the available Network-on-Chip resources and interfaces for data communication are discussed. The concepts of two mechanisms of the data link layer are presented for converting status information into communicable units and for preventing communication resources from being blocked. In the first approach, software-based packet rerouting is proposed. By incorporating information from different layers, this approach provides fault tolerance for deterministic network layer routings. As specialization of software-based rerouting, dimension-order XY rerouting is presented. In the second approach, a reconfigurable routing for Networks-on-Chip with logical hierarchy is proposed in which cross-layer interaction is used to enable hierarchical units to manage themselves autonomously and to reconfigure the routing. Both approaches are evaluated regarding their performance as well as their implementation costs. In a final study, the cross-layer diagnosis technique and cross-layer fault tolerance approaches are combined. The information obtained by the diagnosis technique is used by the fault tolerance approaches for packet rerouting or for routing reconfiguration. The combinations are evaluated regarding their impact on Networks-on-Chip performance. The results show that the crosslayer information exchange with software has a considerable impact on performance when the amount of information becomes too large. In case of crosslayer diagnosis, however, the impact on Networks-on-Chip performance is significantly lower compared to functional and structural diagnosis

    Routing on the Channel Dependency Graph:: A New Approach to Deadlock-Free, Destination-Based, High-Performance Routing for Lossless Interconnection Networks

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    In the pursuit for ever-increasing compute power, and with Moore's law slowly coming to an end, high-performance computing started to scale-out to larger systems. Alongside the increasing system size, the interconnection network is growing to accommodate and connect tens of thousands of compute nodes. These networks have a large influence on total cost, application performance, energy consumption, and overall system efficiency of the supercomputer. Unfortunately, state-of-the-art routing algorithms, which define the packet paths through the network, do not utilize this important resource efficiently. Topology-aware routing algorithms become increasingly inapplicable, due to irregular topologies, which either are irregular by design, or most often a result of hardware failures. Exchanging faulty network components potentially requires whole system downtime further increasing the cost of the failure. This management approach becomes more and more impractical due to the scale of today's networks and the accompanying steady decrease of the mean time between failures. Alternative methods of operating and maintaining these high-performance interconnects, both in terms of hardware- and software-management, are necessary to mitigate negative effects experienced by scientific applications executed on the supercomputer. However, existing topology-agnostic routing algorithms either suffer from poor load balancing or are not bounded in the number of virtual channels needed to resolve deadlocks in the routing tables. Using the fail-in-place strategy, a well-established method for storage systems to repair only critical component failures, is a feasible solution for current and future HPC interconnects as well as other large-scale installations such as data center networks. Although, an appropriate combination of topology and routing algorithm is required to minimize the throughput degradation for the entire system. This thesis contributes a network simulation toolchain to facilitate the process of finding a suitable combination, either during system design or while it is in operation. On top of this foundation, a key contribution is a novel scheduling-aware routing, which reduces fault-induced throughput degradation while improving overall network utilization. The scheduling-aware routing performs frequent property preserving routing updates to optimize the path balancing for simultaneously running batch jobs. The increased deployment of lossless interconnection networks, in conjunction with fail-in-place modes of operation and topology-agnostic, scheduling-aware routing algorithms, necessitates new solutions to solve the routing-deadlock problem. Therefore, this thesis further advances the state-of-the-art by introducing a novel concept of routing on the channel dependency graph, which allows the design of an universally applicable destination-based routing capable of optimizing the path balancing without exceeding a given number of virtual channels, which are a common hardware limitation. This disruptive innovation enables implicit deadlock-avoidance during path calculation, instead of solving both problems separately as all previous solutions

    Dominant designs in complex technological systems - A longitudinal case study of a telecom company 1980-2010

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    The different processes used to innovate and produce successful products and services for companies and define service and even industry architectures ­­­­­­­­­­­­­­­­­­­­­­­­–dominant designs— have received significant scholarly interest. This study sheds light on this process to understand the evolutionary character of dominant designs within complex technological systems.  To do so, it provides longitudinal empirical study of a telecommunications industry and the Nordic case company Sonera from 1980-2010. The units of analysis are Sonera's major businesses, products and strategy that intertwine with industry. To understand the evolution of dominant designs in complex technological systems, theoretical discussion, the management and sociology of technology, an economics perspective, and dynamic capabilities are utilized. The findings identify the key sources of innovation and the processes that drive managers in a multi-product firm to manage its dominant designs successfully. The findings indicate that the likely sources of innovation (and their variations) lead to the rejection of old dominant designs and the emergence of new ones. A key finding is that these sources of innovation produce a shift to a customer/market orientation from a R&D and science orientation as the industry evolves into a more open and horizontal market form. At the same time, the role of the incumbent multi-product firm diminishes, and that of vendors and niche players strengthens. Moreover, the research identifies the most important building blocks that can lead to the successful creation of a new dominant design.  Evidence of change in the relative roles or contributions of various building blocks was seen, depending on the overall life-cycle evolution of the industry and the specific organization. Finally, the role and nature of  firm's products as complex technological systems for shaping the process and outcomes related to dominant designs was seen as important. Instead, new dominant designs emerge in systems characterized by industry convergence when the new technology aligns with the capabilities and incentives of the receiving unit. This study is a rare example of extensive longitudinal data being analyzed both at the company and an industry level in strategic marketing studies. The study thus contributes by creating a framework for the adaptation of dominant designs. The integration of dynamic capabilities, sensing, seizing, and transformation framework to ongoing industry evolution is especially valuable.Erityyppiset innovaatioprosessit jotka tuottavat menestyksekkäitä tuotteita ja palveluita yrityksissä, jopa määrittelevät palvelu ja toimiala-arkkitehtuureja – dominant designeja- ovat herättäneet tutkimuksellista kiinnostusta. Tämä tutkimus valaisee tätä innovaatioprosessia jotta ymmärrys dominant designeista kompleksisten teknologisten systeemien kontekstissa lisääntyy. Tutkimus on historiallinen empiirinen kuvaus telekommunikaatiotoimialasta ja kohdeyritys Sonerasta, Pohjoismaisesta telealan yrityksestä, ajanjaksolla 1980-2010. Analyysikohteet ovat Soneran merkittävimmät liiketoiminnat, tuotteet ja strategia jotka muokkaantuvat vuorovaikutuksessa toimialaevoluution kanssa. Jotta evoluutiota voidaan ymmärtää kompleksisissa teknologisissa systeemeissä seuraavat teoreettiset keskustelut on valittu keskeisiksi: teknologian johtaminen ja sosiologia, taloustieteellinen näkökulma sekä dynaamiset kyvykkyydet. Tutkimuksen löydökset paikallistavat innovaatioiden päälähteet ja prosessit, jotka mahdollistavat yrityksen johdolle dominant designien menestyksekkään hallinnan. Muuttuvat innovaatioiden lähteet ajavat yritykset hylkäämään vanhat dominant designit ja kehittämään uudet. Avainlöydös on että innovaatioiden lähteet muuttuvat asiakas- /markkinaorientointuneiksi tutkimus- ja tiedelähtöisestä samalla kun toimiala kehittyy avoimemmaksi ja horisontaaliseksi. Samaan aikaan vakiintuneen monituoteyrityksen rooli vähenee ja toimittajien/alihankkijoiden sekä 'markkinarakoyritysten (niche)' rooli kasvaa. Lisäksi, tutkimus paikallistaa tärkeimmät tekijät/rakennuspalikat jotka voivat johtaa menestyksekkääseen dominant designin luontiin. Tutkimuksessa havaittiin lisäksi että dominant design rakennuspalikoiden suhteellinen rooli ja vaikutus muuttui toimialan ja yrityksen evoluutiosta johtuen. Lopuksi, dominant designien systeeminen luonne vaikutti innovaatioprosessiin ja lopputuloksiin. Sen sijaan että puhuttaisiin vain yhden tuotteen luonnista, tulee ottaa huomioon toimialan konvergenssi, joka mahdollistaa uuden teknologian omaksumisen ja kaupallistamisen yli teknologisten raja-aitojen. Tämä tutkimus on harvinainen esimerkki laajamittaisesta pitkittäisestä datan analysoinnista yrityksen ja toimialan tasolla strategisen markkinoinnin tutkimusalalla. Tutkimus edistää innovaatioprosessin ymmärrystä luomalla viitekehyksen dominant designien omaksumiseen. Erityisesti dynaamisten kyvykkyyksien integraatio (sensing, seizing, transforming) toimialan evoluutioon on arvokasta

    Designing Change Assimilation Process using Close-up Down Graph for Switch Based Networks

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    In today’s modern switch-based interconnected systems require high performance, reliability and availability. These switch based networks changes their topologies due to hot expansion of components, link or node activation and deactivation. Device failures in high-speed computer networks can also result in topological changes. Also, component failures, addition and deletion of components cause changes in the topology and routing paths supplied by the interconnection network. Therefore a network reconfiguration algorithm must be executed to reestablish the connectivity between the network nodes. Now we have two types of reconfiguration techniques and they are static reconfiguration and dynamic reconfiguration. Static reconfiguration techniques significantly reduce network service since the application traffic is temporally stopped in order to avoid deadlocks. But unfortunately this has negative impact on network service availability. Dynamic network reconfiguration is the process of changing from one routing function to another routing function while the network remains up and running. While performing dynamic network reconfiguration, the main challenge is to avoid deadlocks and provide network service availability along with reduced packet dropping rate. In this paper we demonstrate how dynamic reconfiguration is more efficient than the static reconfiguration for switch based networks

    Reliability and Efficiency of Vehicular Network Applications

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    The DSRC/WAVE initiative is forecast to enable a plethora of applications, classified in two broad types of safety and non-safety applications. In the former type, the reliability performance is of tremendous prominence while, in the latter case, the efficiency of information dissemination is the key driving factor. For safety applications, we adopt a systematic approach to analytically investigate the reliability of the communication system in a symbiotic relationship with the host system comprising a vehicular traffic system and radio propagation environment. To this aim, the¬ interference factor is identified as the central element of the symbiotic relationship. Our approach to the investigation of interference and its impacts on the communication reliability departs from previous studies by the degree of realism incorporated in the host system model. In one dimension, realistic traffic models are developed to describe the vehicular traffic behaviour. In a second dimension, a realistic radio propagation model is employed to capture the unique signal propagation aspects of the host system. We address the case of non-safety applications by proposing a generic framework as a capstone architecture for the development of new applications and the efficiency evaluation of existing ones. This framework, while being independent from networking technology, enables accurate characterization of the various information dissemination tasks that a node performs in cooperation with others. As the central element of the framework, we propose a game theoretic model to describe the interaction of meeting nodes aiming to exchange information of mutual or social interests. An adaptive mechanism is designed to enable a mobile node to measure the social significance of various information topics, which is then used by the node to prioritize the forwarding of information objects
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