4,018 research outputs found

    Automatic generation of human machine interface screens from component-based reconfigurable virtual manufacturing cell

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    Increasing complexity and decreasing time-tomarket require changes in the traditional way of building automation systems. The paper describes a novel approach to automatically generate the Human Machine Interface (HMI) screens for component-based manufacturing cells based on their corresponding virtual models. Manufacturing cells are first prototyped and commissioned within a virtual engineering environment to validate and optimise the control behaviour. A framework for reusing the embedded control information in the virtual models to automatically generate the HMI screens is proposed. Finally, for proof of concept, the proposed solution is implemented and tested on a test rig

    Exploring formal verification methodology for FPGA-based digital systems.

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    Analog Property Checkers: A Ddr2 Case Study

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    The formal specification component of verification can be exported to simulation through the idea of property checkers. The essence of this approach is the automatic construction of an observer from the specification in the form of a program that can be interfaced with a simulator and alert the user if the property is violated by a simulation trace. Although not complete, this lighter approach to formal verification has been effectively used in software and digital hardware to detect errors. Recently, the idea of property checkers has been extended to analog and mixed-signal systems. In this paper, we apply the property-based checking methodology to an industrial and realistic example of a DDR2 memory interface. The properties describing the DDR2 analog behavior are expressed in the formal specification language stl/psl in form of assertions. The simulation traces generated from an actual DDR2 interface design are checked with respect to the stl/psl assertions using the amt tool. The focus of this paper is on the translation of the official (informal and descriptive) specification of two non-trivial DDR2 properties into stl/psl assertions. We study both the benefits and the current limits of such approach

    Specification: The Biggest Bottleneck in Formal Methods and Autonomy

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    Advancement of AI-enhanced control in autonomous systems stands on the shoulders of formal methods, which make possible the rigorous safety analysis autonomous systems require. An aircraft cannot operate autonomously unless it has design-time reasoning to ensure correct operation of the autopilot and runtime reasoning to ensure system health management, or the ability to detect and respond to off-nominal situations. Formal methods are highly dependent on the specifications over which they reason; there is no escaping the “garbage in, garbage out” reality. Specification is difficult, unglamorous, and arguably the biggest bottleneck facing verification and validation of aerospace, and other, autonomous systems. This VSTTE invited talk and paper examines the outlook for the practice of formal specification, and highlights the on-going challenges of specification, from design-time to runtime system health management. We exemplify these challenges for specifications in Linear Temporal Logic (LTL) though the focus is not limited to that specification language. We pose challenge questions for specification that will shape both the future of formal methods, and our ability to more automatically verify and validate autonomous systems of greater variety and scale. We call for further research into LTL Genesis
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