Design, processing and testing of LSI arrays hybrid microelectronics task

Those factors affecting the cost of electronic subsystems utilizing LSI microcircuits were determined and the most efficient methods for low cost packaging of LSI devices as a function of density and reliability were developed

Conference Report: Hierarchical Design Stressed at Design Automation Conference

Until recently the general attitude of engineers to design automation was confused–they questioned its value yet deplored its limited availability. To increase the amount of DA knowledge in the public domain, the 15th in the series of Annual Design Automation Conferences was held June 19-21 at Caesar's Palace, Las Vegas. Due either to this enlightened choice of venue or to spreading paranoia over handling VLSI designs, this year's conference was extremely well attended–650 delegates, an increase of 50 percent over last year. However, for those expecting ing to learn of new tools for survival in technologies governed by Moore's Laws, this conference may have been somewhat disappointing. It was largely more of the same–PWB layout, testing, IC layout, design languages, logic design, simulation, CAM, and graphics

Second year technical report on-board processing for future satellite communications systems

Advanced baseband and microwave switching techniques for large domestic communications satellites operating in the 30/20 GHz frequency bands are discussed. The nominal baseband processor throughput is one million packets per second (1.6 Gb/s) from one thousand T1 carrier rate customer premises terminals. A frequency reuse factor of sixteen is assumed by using 16 spot antenna beams with the same 100 MHz bandwidth per beam and a modulation with a one b/s per Hz bandwidth efficiency. Eight of the beams are fixed on major metropolitan areas and eight are scanning beams which periodically cover the remainder of the U.S. under dynamic control. User signals are regenerated (demodulated/remodulated) and message packages are reformatted on board. Frequency division multiple access and time division multiplex are employed on the uplinks and downlinks, respectively, for terminals within the coverage area and dwell interval of a scanning beam. Link establishment and packet routing protocols are defined. Also described is a detailed design of a separate 100 x 100 microwave switch capable of handling nonregenerated signals occupying the remaining 2.4 GHz bandwidth with 60 dB of isolation, at an estimated weight and power consumption of approximately 400 kg and 100 W, respectively

The 30/20 GHz flight experiment system, phase 2. Volume 1: Executive summary

Summary information on the final communication system design, communication payload, space vehicle, and development plan for the 30/20 GHz flight experiment will be installed on the LEASAT spacecraft which will be placed into orbit from the space shuttle cargo bay. The communication concept has two parts: a truck service and a customer premise service (CPS). The trucking system serves four spot beams which are interconnected in a satellite switched time division multiple access mode by an IF switch matrix. The CPS covers two large areas of the eastern United States with a pair of scanning beams

The 30/20 GHz flight experiment system, phase 2. Volume 2: Experiment system description

A detailed technical description of the 30/20 GHz flight experiment system is presented. The overall communication system is described with performance analyses, communication operations, and experiment plans. Hardware descriptions of the payload are given with the tradeoff studies that led to the final design. The spacecraft bus which carries the payload is discussed and its interface with the launch vehicle system is described. Finally, the hardwares and the operations of the terrestrial segment are presented

Data systems elements technology assessment and system specifications, issue no. 1

The ability to satisfy the objectives of future NASA Office of Applications Programs is dependent on technology advances in a number of areas of data systems. The technology of end-to-end data systems (space generator elements through ground processing, dissemination, and presentation, is examined in terms of state of the art, trends, and projected developments in the 1980 to 1985 timeframe. Capability is considered in terms of elements that are either commercially available or that can be implemented from commercially available components with minimal development

Ultramicrowave communications system, phase 3

The ultramicrowave communications system program investigated the feasibility of a solid state system that meets the projected space to space requirements, while using the advantages of the 100 to 200 GHz band. The program successfully demonstrated a laboratory model of a high frequency communications system operating between 100 to 200 GHz. In the process, vendor claims for performance specifications of discrete components were evaluated, and a window was provided into system design and integration problems

Advanced modulation technology development for earth station demodulator applications. Coded modulation system development

A jointly optimized coded modulation system is described which was designed, built, and tested by COMSAT Laboratories for NASA LeRC which provides a bandwidth efficiency of 2 bits/s/Hz at an information rate of 160 Mbit/s. A high speed rate 8/9 encoder with a Viterbi decoder and an Octal PSK modem are used to achieve this. The BER performance is approximately 1 dB from the theoretically calculated value for this system at a BER of 5 E-7 under nominal conditions. The system operates in burst mode for downlink applications and tests have demonstrated very little degradation in performance with frequency and level offset. Unique word miss rate measurements were conducted which demonstrate reliable acquisition at low values of Eb/No. Codec self tests have verified the performance of this subsystem in a stand alone mode. The codec is capable of operation at a 200 Mbit/s information rate as demonstrated using a codec test set which introduces noise digitally. The measured performance is within 0.2 dB of the computer simulated predictions. A gate array implementation of the most time critical element of the high speed Viterbi decoder was completed. This gate array add-compare-select chip significantly reduces the power consumption and improves the manufacturability of the decoder. This chip has general application in the implementation of high speed Viterbi decoders