A baseband wireless spectrum hypervisor for multiplexing concurrent OFDM signals

The next generation of wireless and mobile networks will have to handle a significant increase in traffic load compared to the current ones. This situation calls for novel ways to increase the spectral efficiency. Therefore, in this paper, we propose a wireless spectrum hypervisor architecture that abstracts a radio frequency (RF) front-end into a configurable number of virtual RF front ends. The proposed architecture has the ability to enable flexible spectrum access in existing wireless and mobile networks, which is a challenging task due to the limited spectrum programmability, i.e., the capability a system has to change the spectral properties of a given signal to fit an arbitrary frequency allocation. The proposed architecture is a non-intrusive and highly optimized wireless hypervisor that multiplexes the signals of several different and concurrent multi-carrier-based radio access technologies with numerologies that are multiple integers of one another, which are also referred in our work as radio access technologies with correlated numerology. For example, the proposed architecture can multiplex the signals of several Wi-Fi access points, several LTE base stations, several WiMAX base stations, etc. As it able to multiplex the signals of radio access technologies with correlated numerology, it can, for instance, multiplex the signals of LTE, 5G-NR and NB-IoT base stations. It abstracts a radio frequency front-end into a configurable number of virtual RF front ends, making it possible for such different technologies to share the same RF front-end and consequently reduce the costs and increasing the spectral efficiency by employing densification, once several networks share the same infrastructure or by dynamically accessing free chunks of spectrum. Therefore, the main goal of the proposed approach is to improve spectral efficiency by efficiently using vacant gaps in congested spectrum bandwidths or adopting network densification through infrastructure sharing. We demonstrate mathematically how our proposed approach works and present several simulation results proving its functionality and efficiency. Additionally, we designed and implemented an open-source and free proof of concept prototype of the proposed architecture, which can be used by researchers and developers to run experiments or extend the concept to other applications. We present several experimental results used to validate the proposed prototype. We demonstrate that the prototype can easily handle up to 12 concurrent physical layers

Control and evaluation of the ad-fmcomms5-ebz software-defined radio

Software-defined radios (SDR) have presented a new way to do telecommunication systems in a configurable, efficient and portable manner. With the rapid evolving capabilities of these systems, the traditional non-software-configurable ones are being left behind. This project explores the concept of software-defined radio in a theoretical and practical way using the ADFMComms5-EBZ, a SDR provided by Analog Devices with 4 transceivers. A complete analysis is done on the AD-FMComms5-EBZ, understanding all its physical components and its digital interface that make it software-configurable. Furthemore, its interaction with MATLAB/Simulink and with the IIO Oscilloscope application is studied, providing a profound explanation of the board's capabilities on these software. Finally, a few algorithms we found interesting are designed with MATLAB to enable all the potential of the board by reaching MIMO capabilities, analysing the phase of each transmitter and the reception order of symbols.Les ràdios definides per software (SDR) s'han presentat com a una nova manera de fer sistemes de telecomunicacions gràcies a la seva configurabilitat, eficiència i portabilitat. La seva evolució ha sigut ràpida i contínua, fent que els sistemes tradicionals que no son configurables en software s'hagin quedat enrere. Aquest projecte explora el concepte de ràdio definida per software de forma teòrica i pràctica utilitzant l'AD-FMComms5-EBZ, una SDR dissenyada per Analog Devices que incorpora 4 transceptors. En el projecte s'hi fa una anàlisi completa de l'AD-FMComms5-EBZ, entenent tots els seus components físics i la seva interfície digital que en permet la configurabilitat per via de software dels seus components. A més, s'estudia la seva interacció amb MATLAB/Simulink i amb l'aplicació IIO Oscilloscope, donant una explicació profusa de les capacitats de la placa amb aquest programari. Finalment, es dissenyen alguns algoritmes que hem trobat interessants amb MATLAB per a habilitar tot el potencial de la placa, aconseguint que funcioni com a un sistema MIMO, analitzant la fase ens els diferents transmissors i l'ordre de la recepció dels símbols.Las radios definidas por software (SDR) se han presentado como una nueva manera de hacer sistemas de telecomunicaciones gracias a su configurabilidad, eficiencia y portabilidad. Su evolución ha sido rápida y continua, haciendo que los sistemas tradicionales que no son configurables en software se hayan quedado atrás. Este proyecto explora el concepto de radio definida por software de forma teórica y práctica utilizando el AD-FMComms5-EBZ, una SDR diseñada por Analog Devices que incorpora 4 transceptores. En el proyecto se hace un análisis completo de la AD-FMComms5-EBZ, entendiendo todos sus componentes físicos y su interfaz digital que permite su configurabilidad por vía de software de sus componentes. Además, se estudia su interacción con MATLAB / Simulink y con la aplicación IIO Oscilloscope, dando una explicación profusa de las capacidades de la placa con este software. Finalmente, se diseñan algunos algoritmos que hemos encontrado interesantes con MATLAB para habilitar todo el potencial de la placa, consiguiendo que funcione como un sistema MIMO, analizando la fase en los diferentes transmisores y el orden de la recepción de los símbolos

SdrLift: A Domain-Specific Intermediate Hardware Synthesis Framework for Prototyping Software-Defined Radios

Modern design of Software-Defined Radio (SDR) applications is based on Field Programmable Gate Arrays (FPGA) due to their ability to be configured into solution architectures that are well suited to domain-specific problems while achieving the best trade-off between performance, power, area, and flexibility. FPGAs are well known for rich computational resources, which traditionally include logic, register, and routing resources. The increased technological advances have seen FPGAs incorporating more complex components that comprise sophisticated memory blocks, Digital Signal Processing (DSP) blocks, and high-speed interfacing to Gigabit Ethernet (GbE) and Peripheral Component Interconnect Express (PCIe) bus. Gateware for programming FPGAs is described at a lowlevel of design abstraction using Register Transfer Language (RTL), typically using either VHSIC-HDL (VHDL) or Verilog code. In practice, the low-level description languages have a very steep learning curve, provide low productivity for hardware designers and lack readily available open-source library support for fundamental designs, and consequently limit the design to only hardware experts. These limitations have led to the adoption of High-Level Synthesis (HLS) tools that raise design abstraction using syntax, semantics, and software development notations that are well-known to most software developers. However, while HLS has made programming of FPGAs more accessible and can increase the productivity of design, they are still not widely adopted in the design community due to the low-level skills that are still required to produce efficient designs. Additionally, the resultant RTL code from HLS tools is often difficult to decipher, modify and optimize due to the functionality and micro-architecture that are coupled together in a single High-Level Language (HLL). In order to alleviate these problems, Domain-Specific Languages (DSL) have been introduced to capture algorithms at a high level of abstraction with more expressive power and providing domain-specific optimizations that factor in new transformations and the trade-off between resource utilization and system performance. The problem of existing DSLs is that they are designed around imperative languages with an instruction sequence that does not match the hardware structure and intrinsics, leading to hardware designs with system properties that are unconformable to the high-level specifications and constraints. The aim of this thesis is, therefore, to design and implement an intermediatelevel framework namely SdrLift for use in high-level rapid prototyping of SDR applications that are based on an FPGA. The SdrLift input is a HLL developed using functional language constructs and design patterns that specify the structural behavior of the application design. The functionality of the SdrLift language is two-fold, first, it can be used directly by a designer to develop the SDR applications, secondly, it can be used as the Intermediate Representation (IR) step that is generated by a higher-level language or a DSL. The SdrLift compiler uses the dataflow graph as an IR to structurally represent the accelerator micro-architecture in which the components correspond to the fine-level and coarse-level Hardware blocks (HW Block) which are either auto-synthesized or integrated from existing reusable Intellectual Property (IP) core libraries. Another IR is in the form of a dataflow model and it is used for composition and global interconnection of the HW Blocks while making efficient interfacing decisions in an attempt to satisfy speed and resource usage objectives. Moreover, the dataflow model provides rules and properties that will be used to provide a theoretical framework that formally analyzes the characteristics of SDR applications (i.e. the throughput, sample rate, latency, and buffer size among other factors). Using both the directed graph flow (DFG) and the dataflow model in the SdrLift compiler provides two benefits: an abstraction of the microarchitecture from the high-level algorithm specifications and also decoupling of the microarchitecture from the low-level RTL implementation. Following the IR creation and model analyses is the VHDL code generation which employs the low-level optimizations that ensure optimal hardware design results. The code generation process per forms analysis to ensure the resultant hardware system conforms to the high-level design specifications and constraints. SdrLift is evaluated by developing representative SDR case studies, in which the VHDL code for eight different SDR applications is generated. The experimental results show that SdrLift achieves the desired performance and flexibility, while also conserving the hardware resources utilized

Cognitive Radio Programming: Existing Solutions and Open Issues

Software defined radio (sdr) technology has evolved rapidly and is now reaching market maturity, providing solutions for cognitive radio applications. Still, a lot of issues have yet to be studied. In this paper, we highlight the constraints imposed by recent radio protocols and we present current architectures and solutions for programming sdr. We also list the challenges to overcome in order to reach mastery of future cognitive radios systems.La radio logicielle a évolué rapidement pour atteindre la maturité nécessaire pour être mise sur le marché, offrant de nouvelles solutions pour les applications de radio cognitive. Cependant, beaucoup de problèmes restent à étudier. Dans ce papier, nous présentons les contraintes imposées par les nouveaux protocoles radios, les architectures matérielles existantes ainsi que les solutions pour les programmer. De plus, nous listons les difficultés à surmonter pour maitriser les futurs systèmes de radio cognitive

Design and implementation of an OFDM-based communication system for the GNU Radio platform

Projecte final de carrera fet en col.laboració amb Institut für Kommunikationsnetze und Rechnersysteme. Universität StuttgartCatalà: El processament de senyal en temps real mitjançant software és un camp que s'està expandint molt gràcies a la capacitat de processament dels ordinadors actuals. L'objectiu d'aquest treball ha estat el disseny i la implementació d'una Ràdio Definida en Software (SDR) que funcioni amb tecnologia OFDM, similar a la utilitzada en les comunicacions mòvils de 4a generació, per a la plataforma GNU Radio.Castellano: El procesado de señal en tiempo real mediante software es un campo en expansión gracias a la capacidad de computación de los ordenadores actuales. El objetivo de este trabajo ha sido el diseño y la implementación de una Radio Definida en Software (SDR) que funcione con tecnología OFDM, similar a la utilizada en las comunicaciones móviles de 4ª generación, para la plataforma GNU Radio.English: Software based real time signal processing is a field in expansion thanks to the computing capacity of actual personal computers. The objective of this work is the design and the implementation of a Software Defined Radio (SDR) that uses OFDM technology, which is the one used in the 4th generation of wireless communications

Precise Packet Loss Pattern Generation by Intentional Interference

Abstract—Intermediate-quality links often cause vulnerable connectivity in wireless sensor networks, but packet losses caused by such volatile links are not easy to trace. In order to equip link layer protocol designers with a reliable test and debugging tool, we develop a reactive interferer to generate packet loss patterns precisely. By using intentional interference to emulate parameterized lossy links with very low intrusiveness, our tool facilitates both robustness evaluation of protocols and flaw detection in protocol implementation

Prototype mixed-signal hardware for public safety radio interoperability

In performing their required duties public safety personnel from differing departments often need to communicate with one another using their in-car radios. However, in many cases, especially involving small departments, this interoperability doesn\u27t exist. A prototype circuit design has been developed and tested within the laboratory using two common radio systems: EFJohnson and Motorola. The preliminary results have shown successful operation as a system gateway between the two radio systems with good performance regarding audio signal latency and minimizing the push-to-talk signal generation delay

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve