MISSED: an environment for mixed-signal microsystem testing and diagnosis

A tight link between design and test data is proposed for speeding up test-pattern generation and diagnosis during mixed-signal prototype verification. Test requirements are already incorporated at the behavioral level and specified with increased detail at lower hierarchical levels. A strict distinction between generic routines and implementation data makes reuse of software possible. A testability-analysis tool and test and DFT libraries support the designer to guarantee testability. Hierarchical backtrace procedures in combination with an expert system and fault libraries assist the designer during mixed-signal chip debuggin

RON-BEAM DEBUG AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS

A current research project at IMAG/TIM3 Laboratory aims at an integrated test system combining the use of the Scanning Electron Microscope (SEM), used in voltage contrast mode, with a new high-level approach of fault location in complex VLSI circuits, in order to reach a complete automated diagnosis process. Two research themes are induced by this project, which are: prototype validation of known circuits, on which CAD information is available, and failure analysis of unknown circuits, which are compared to reference circuits. For prototype validation, a knowledge-based approach to fault location is used. Concerning failure analysis, automatic image comparison based on pattern recog- nition techniques is performed. The purpose of the paper is to present these two methodologies, focusing on the SEM-based data acquisition process

Advanced Scanning Electron Microscopy Methods and Applications to Integrated Circuit Failure Analysis

Semiconductor device failure analysis using the scanning electron microscope (SEM) has become a standard component of integrated circuit fabrication. Improvements in SEM capabilities and in digital imaging and processing have advanced standard acquisition modes and have promoted new failure analysis methods. The physical basis of various data acquisition modes, both standard and new, and their implementation on a computer controlled SEM image acquisition/processing system are discussed, emphasizing the advantages of each method. Design considerations for an integrated, online failure analysis system are also described. Recent developments in the integration of the information provided by electron beam analysis, conventional integrated circuit (IC) testing, computer-aided design (CAD), and device parameter testing into a single system promise to provide powerful future tools for failure analysis

Semiconductor technology program: Progress briefs

Measurement technology for semiconductor materials, process control, and devices, is discussed. Silicon and silicon based devices are emphasized. Highlighted activities include semiinsulating GaAs characterization, an automatic scanning spectroscopic ellipsometer, linewidth measurement and coherence, bandgap narrowing effects in silicon, the evaluation of electrical linewidth uniformity, and arsenicomplanted profiles in silicon

Electron Beam Induced Damage on Passivated Metal Oxide Semiconductor Devices

Electron beam testing of integrated circuits (IC) is currently based on the electron beam induced conductivity in insulators to short the passivation layer and to enable a voltage measurement at covered conductor tracks. However, applying this technique to passivated MOS devices causes severe radiation damage, which was at first explained by primary electrons penetrating into the deep-lying gate oxide. Nondestructive electron beam testing was expected by using low electron energies that do not allow the primary electrons to reach into the gate oxide. Therefore here the influence of nonpenetrating electron irradiation on the characteristics of passivated NMOS transistors has been studied. The experiments demonstrate that significant damage is caused even when primary electrons do not reach into the gate oxide. This can be explained by secondary X-rays, generated by the primary electrons in the upper layers, that then penetrate into the gate oxide. Radiation damage increases with irradiation dose, primary energy and with decreasing gate size. Though using the lowest primary electron energy possible to build up the necessary conductive channel, even low irradiation doses alter the devices drastically. Only by blanking off the high energy electron beam at gate oxide areas during the scan, i.e. by application of the window scan mode, is a nearly nondestructive testing of passivated MOS devices via the electron beam induced conductivity made possible. Another possibility to decrease radiation damage is the reduction of primary electron energy to about 1 keV. Then electron beam testing is no longer based on the physics of electron beam induced conductivity, but on the capacitive coupling voltage contrast

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

Index to 1984 NASA Tech Briefs, volume 9, numbers 1-4

Short announcements of new technology derived from the R&D activities of NASA are presented. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This index for 1984 Tech B Briefs contains abstracts and four indexes: subject, personal author, originating center, and Tech Brief Number. The following areas are covered: electronic components and circuits, electronic systems, physical sciences, materials, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences