System-Level Design for Nano-Electronics

Latest fabrication technologies of self-assembly nano-circuits (carbon nanotubes, silicon nanowires, etc.) have deployed bottom-up techniques that reach feature sizes well below 65nm, holding great promise for future large silicon-based integrated circuits. However, new nano-devices intrinsically have much higher failure rates than CMOS-based ones. Thus, new design methodologies must address the combination of devicelevel error-prone technologies with system integration constraints (low power, performance) to deliver competitive devices at the nanometer scale. In this paper we show that a very promising way to achieve nano-scale devices is combining imperfection-aware design techniques during fabrication with gate defect modeling at circuit level. Our results using this approach to define a Carbon Nanotube Field-Effect Transistor (CNFET)-based design flow for nanoscale logic circuits attain more than 3x energy-delay-product advantage compared to 65nm CMOS-based ones

Programmable Logic Circuits based on Ambipolar CNFET

Recently, it was demonstrated that the polarity of carbon nanotube field effect transistors can be electrically controlled. In this paper we show how Programmable Logic Arrays (PLA) can be built out of these devices, and we illustrate how they outperform usual PLA by internal signal inversion. The simulations show an area saving up to approximately 21% and decrease of the delay in PLA-based FPGA by 50%. We also show that this architecture is suitable for high-performance design tools and defect-tolerance approaches

Robust Circuit & Architecture Design in the Nanoscale Regime

Silicon based integrated circuit (IC) technology is approaching its physical limits. For sub 10nm technology nodes, the carbon nanotube (CNT) based field effect transistor has emerged as a promising device because of its excellent electronic properties. One of the major challenges faced by the CNT technology is the unwanted growth of metallic tubes. At present, there is no known CNT fabrication technology which allows the fabrication of 100% semiconducting CNTs. The presence of metallic tubes creates a short between the drain and source terminals of the transistor and has a detrimental impact on the delay, static power and yield of CNT based gates. This thesis will address the challenge of designing robust carbon nanotube based circuits in the presence of metallic tubes. For a small percentage of metallic tubes, circuit level solutions are proposed to increase the functional yield of CNT based gates in the presence of metallic tubes. Accurate analytical models with less than a 3% inaccuracy rate are developed to estimate the yield of CNT based circuit for a different percentage of metallic tubes and different drive strengths of logic gates. Moreover, a design methodology is developed for yield-aware carbon nanotube based circuits in the presence of metallic tubes using different CNFET transistor configurations. Architecture based on regular logic bricks with underlying hybrid CNFET configurations are developed which gives better trade-offs in terms of performance, power, and functional yield. In the case when the percentage of metallic tubes is large, the proposed circuit level techniques are not sufficient. Extra processing techniques must be applied to remove the metallic tubes. The tube removal techniques have trade-offs, as the removal process is not perfect and removes semiconducting tubes in addition to removing unwanted metallic tubes. As a result, stochastic removal of tubes from the drive and fanout gate(s) results in large variation in the performance of CNFET based gates and in the worst case open circuit gates. A Monte Carlo simulation engine is developed to estimate the impact of the removal of tubes on the performance and power of CNFET based logic gates. For a quick estimation of functional yield of logic gates, accurate analytical models are developed to estimate the functional yield of logic gates when a fraction of the tubes are removed. An efficient tube level redundancy (TLR) is proposed, resulting in a high functional yield of carbon nanotube based circuits with minimal overheads in terms of area and power when large fraction of tubes are removed. Furthermore, for applications where parallelism can be utilized we propose to increase the functional yield of the CNFET based circuits by increasing the logic depth of gates

Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis

This paper exploits the unique in-field controllability of the device polarity of ambipolar carbon nanotube field effect transistors (CNTFETs) to design a technology library with higher expressive power than conventional CMOS libraries. Based on generalized NOR-NAND-AOI-OAI primitives, the proposed library of static ambipolar CNTFET gates efficiently implements XOR functions, provides full-swing outputs, and is extensible to alternate forms with area-performance tradeoffs. Since the design of the gates can be regularized, the ability to functionalize them in-field opens opportunities for novel regular fabrics based on ambipolar CNTFETs. Technology mapping of several multi-level logic benchmarks — including multipliers, adders, and linear circuits — indicates that on average, it is possible to reduce both the number of gates and area by ∼ 38% while also improving performance by 6.9×

Investigations of Carbon Nanotube Based Electronic Devices with Focus on Metal and Carbon Nanotube Contacts

Ph.DDOCTOR OF PHILOSOPH

An Outlook on Design Technologies for Future Integrated Systems

The economic and social demand for ubiquitous and multifaceted electronic systems-in combination with the unprecedented opportunities provided by the integration of various manufacturing technologies-is paving the way to a new class of heterogeneous integrated systems, with increased performance and connectedness and providing us with gateways to the living world. This paper surveys design requirements and solutions for heterogeneous systems and addresses design technologies for realizing them

Excellentia Eminentia Effectio

"In these pages you will learn about the fascinating research endeavors that each of our faculty members is undertaking. We have divided their research into the broad categories of health, sustainability, information, and systems. While we recognize the imperfect nature of categorizing research that, by its very nature may be interdisciplinary or transdisciplinary, we nonetheless believe it will be helpful as a way to see the depth and breadth of our research endeavors within each grouping. As you read the profiles on these pages, I know you will begin to appreciate that, taken as a whole, the research spectrum at Columbia Engineering is exceptional and that, as our professors go about their work, they are at the cusp of making breakthroughs that will have a major impact on the way we live our lives today and tomorrow.

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book