1,394 research outputs found

    Microcomputer based controller for the Langley 0.3-meter Transonic Cryogenic Tunnel

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    Flow control of the Langley 0.3-meter Transonic Cryogenic Tunnel (TCT) is a multivariable nonlinear control problem. Globally stable control laws were generated to hold tunnel conditions in the presence of geometrical disturbances in the test section and precisely control the tunnel states for small and large set point changes. The control laws are mechanized as four inner control loops for tunnel pressure, temperature, fan speed, and liquid nitrogen supply pressure, and two outer loops for Mach number and Reynolds number. These integrated control laws have been mechanized on a 16-bit microcomputer working on DOS. This document details the model of the 0.3-m TCT, control laws, microcomputer realization, and its performance. The tunnel closed loop responses to small and large set point changes were presented. The controller incorporates safe thermal management of the tunnel cooldown based on thermal restrictions. The controller was shown to provide control of temperature to + or - 0.2K, pressure to + or - 0.07 psia, and Mach number to + or - 0.002 of a given set point during aerodynamic data acquisition in the presence of intrusive geometrical changes like flexwall movement, angle-of-attack changes, and drag rake traverse. The controller also provides a new feature of Reynolds number control. The controller provides a safe, reliable, and economical control of the 0.3-m TCT

    A Low-Power Silicon-Photomultiplier Readout ASIC for the CALICE Analog Hadronic Calorimeter

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    The future e + e − collider experiments, such as the international linear collider, provide precise measurements of the heavy bosons and serve as excellent tests of the underlying fundamental physics. To reconstruct these bosons with an unprecedented resolution from their multi-jet final states, a detector system employing the particle flow approach has been proposed, requesting calorimeters with imaging capabilities. The analog hadron calorimeter based on the SiPM-on-tile technology is one of the highly granular candidates of the imaging calorimeters. To achieve the compactness, the silicon-photomultiplier (SiPM) readout electronics require a low-power monolithic solution. This thesis presents the design of such an application-specific integrated circuit (ASIC) for the charge and timing readout of the SiPMs. The ASIC provides precise charge measurement over a large dynamic range with auto-triggering and local zero-suppression functionalities. The charge and timing information are digitized using channel-wise analog-to-digital and time-to-digital converters, providing a fully integrated solution for the SiPM readout. Dedicated to the analog hadron calorimeter, the power-pulsing technique is applied to the full chip to meet the stringent power consumption requirement. This work also initializes the commissioning of the calorimeter layer with the use of the designed ASIC. An automatic calibration procedure has been developed to optimized the configuration settings for the chip. The new calorimeter base unit with the designed ASIC has been produced and its functionality has been tested

    A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

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    © 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

    Readout Method And Electronic Bandwidth Control For A Silicon In-plane Tuning Fork Gyroscope

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    Disclosed are methods and a sensor architecture that utilizes the residual quadrature error in a gyroscope to achieve and maintain perfect mode-matching, i.e., ~0 Hz split between the drive and sense mode frequencies, and to electronically control sensor bandwidth. In a reduced-to-practice embodiment, a 6 mW, 3V CMOS ASIC and control algorithm are interfaced to a mode-matched MEMS tuning fork gyroscope to implement an angular rate sensor with bias drift as low as 0.15°/hr and angle random walk of 0.003°/√hr, which is the lowest recorded to date for a silicon MEMS gyroscope. The system bandwidth can be configured between 0.1 Hz and 1 kHz.Georgia Tech Research Coporatio

    Iterrative correction of measurement with averaging of dithered samples

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    Self-calibration techniques could eliminate measurement errors caused by time changes and component aging. For ADC performance enhancement also averaging is necessary. In the paper the iterative measurement error correction method is presented in combination with averaging. Dither theory for Gaussian noise has been used for exhibition of averaging abilities in ADC characteristic improvement. Experimental ENOB value improvement is more than 1.5 bit

    All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters

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    The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic Split-ADC calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the Split-ADC method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 Split-TI converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the Split-SAR method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples

    Systems and Methods for the Spectral Calibration of Swept Source Optical Coherence Tomography Systems

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    This dissertation relates to the transition of the state of the art of swept source optical coherence tomography (SS-OCT) systems to a new realm in which the image acquisition speed is improved by an order of magnitude. With the aid of a better quality imaging technology, the speed-up factor will considerably shorten the eye-exam clinical visits which in turn improves the patient and doctor interaction experience. These improvements will directly lower associated medical costs for eye-clinics and patients worldwide. There are several other embodiments closely related to Optical Coherence Tomography (OCT) that could benefit from the ideas presented in this dissertation including: optical coherence microscopy (OCM), full-field OCT (FF-OCT), optical coherence elastography (OCE), optical coherence tomography angiography (OCT-A), anatomical OCT (aOCT), optical coherence photoacoustic microscopy (OC-PAM), micro optical coherence tomography (µ OCT), among others. In recent decades, OCT has established itself as the de-facto imaging process that most ophthalmologists refer to in their clinical practices. In a broader sense, optical coherence tomography is used in applications when low penetration and high resolution are desired. These applications include different fields of biomedical sciences including cardiology, dermatology, and pulmonary related sciences. Many other industrial applications including quality control and precise measurements have also been reported that are related to the OCT technology. Every new iteration of OCT technology has always come about with advanced signal processing and data acquisition algorithms using mixed-signal architectures, calibration and signal processing techniques. The existing industrial practices towards data acquisition, processing, and image creation relies on conventional signal processing design flows, which extensively employ continuous/discrete techniques that are both time-consuming and costly. The ideas presented in this dissertation can take the technology to a new dimension of quality of service

    Energy Efficient Pipeline ADCs Using Ring Amplifiers

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    Pipeline ADCs require accurate amplification. Traditionally, an operational transconductance amplifier (OTA) configured as a switched-capacitor (SC) amplifier performs such amplification. However, traditional OTAs limit the power efficiency of ADCs since they require high quiescent current for slewing and bandwidth. In addition, it is difficult to design low-voltage OTAs in modern, scaled CMOS. The ring amplifier is an energy efficient and high output swing alternative to an OTA for SC circuits which is basically a three-stage inverter amplifier stabilized in a feedback configuration. However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation. In this dissertation, three types of innovative ring amplifiers are presented and verified with state-of-the-art energy efficient pipeline ADCs. These new ring amplifiers overcome the limitations of the conventional ring amplifier and further improve energy efficiency. The first topic of this dissertation is a self-biased ring amplifier that makes the ring amplifier more practical and power efficient, while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing. In addition, the ring amplifiers are also used as comparators in the 1.5b sub-ADCs by utilizing the unique characteristics of the ring amplifier. This removes the need for dedicated comparators in sub-ADCs, thus further reducing the power consumption of the ADC. The prototype 10.5b 100 MS/s comparator-less pipeline ADC with the self-biased ring amplifiers has measured SNDR, SNR and SFDR of 56.6 dB (9.11b), 57.5 dB and 64.7 dB, respectively, and consumes 2.46 mW, which results in Walden Figure-of-Merit (FoM) of 46.1 fJ/ conversion∙step. The second topic is a fully-differential ring amplifier, which solves the problems of single-ended ring amplifiers while maintaining the benefits of the single-ended ring amplifiers. This differential ring-amplifier is applied in a 13b 50 MS/s SAR-assisted pipeline ADC. Furthermore, an improved capacitive DAC switching method for the first stage SAR reduces the DAC linearity errors and switching energy. The prototype ADC achieves measured SNDR, SNR and SFDR of 70.9 dB (11.5b), 71.3 dB and 84.6 dB, respectively, and consumes 1 mW. This measured performance is equivalent to Walden and Schreier FoMs of 6.9 fJ/conversion∙step and 174.9 dB, respectively. Finally, a four-stage fully-differential ring amplifier improves the small-signal gain to over 90 dB without compromising speed. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. This is more area efficient than the conventional auto-zero noise folding reduction technique. A systematic mismatch free SAR CDAC layout method is also presented. The prototype 15b 100 MS/s calibration-free SAR-assisted pipeline ADC using the four-stage ring amplifier achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting in Schreier FoM of 176.6 dB.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138759/1/yonglim_1.pd
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