DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

A programmable BIST architecture for clusters of Multiple-Port SRAMs

This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timin

Why Extension-Based Proofs Fail

We introduce extension-based proofs, a class of impossibility proofs that includes valency arguments. They are modelled as an interaction between a prover and a protocol. Using proofs based on combinatorial topology, it has been shown that it is impossible to deterministically solve k-set agreement among n > k > 1 processes in a wait-free manner in certain asynchronous models. However, it was unknown whether proofs based on simpler techniques were possible. We show that this impossibility result cannot be obtained for one of these models by an extension-based proof and, hence, extension-based proofs are limited in power.Comment: This version of the paper is for the NIS model. Previous versions of the paper are for the NIIS mode

A digital high-dynamic-range CMOS image sensor with multi-integration and pixel readout request

A novel principle has been developed to build an ultra wide dynamic range digital CMOS image sensor. Multiple integrations are used to achieve the required dynamic. Its innovative readout system allows a direct capture of the final image from the different exposure time with no need of external reconstruction. The sensor readout system is entirely digital, implementing an in-pixel ADC. Realized in the STMicroelectronics 0.13μm CMOS standard technology, the 10μm x 10μm pixels contain 42 transistors with a fill factor of 25%. The sensor is able to capture more than 120dB dynamic range scenes at video rate

Theano: new features and speed improvements

Theano is a linear algebra compiler that optimizes a user's symbolically-specified mathematical computations to produce efficient low-level implementations. In this paper, we present new features and efficiency improvements to Theano, and benchmarks demonstrating Theano's performance relative to Torch7, a recently introduced machine learning library, and to RNNLM, a C++ library targeted at recurrent neural networks.Comment: Presented at the Deep Learning Workshop, NIPS 201

A Reconfigurable Mixed-signal Implementation of a Neuromorphic ADC

We present a neuromorphic Analogue-to-Digital Converter (ADC), which uses integrate-and-fire (I&F) neurons as the encoders of the analogue signal, with modulated inhibitions to decohere the neuronal spikes trains. The architecture consists of an analogue chip and a control module. The analogue chip comprises two scan chains and a twodimensional integrate-and-fire neuronal array. Individual neurons are accessed via the chains one by one without any encoder decoder or arbiter. The control module is implemented on an FPGA (Field Programmable Gate Array), which sends scan enable signals to the scan chains and controls the inhibition for individual neurons. Since the control module is implemented on an FPGA, it can be easily reconfigured. Additionally, we propose a pulse width modulation methodology for the lateral inhibition, which makes use of different pulse widths indicating different strengths of inhibition for each individual neuron to decohere neuronal spikes. Software simulations in this paper tested the robustness of the proposed ADC architecture to fixed random noise. A circuit simulation using ten neurons shows the performance and the feasibility of the architecture.Comment: BioCAS-201

A high dynamic range digital LinLog CMOS image sensor architecture based on Event Readout of pixels and suitable for low voltage operation

Several approaches have been developed to extend the dynamic range of image sensor in order to keep all the information content of natural scenes covering a very broad range of illumination. Digital CMOS image sensor are especially well suited to wide dynamic range imaging by implementing dual sampling, multiple exposure methods using either column or in pixel ADC, or Address Event Representation. A new architecture of digital high dynamic range CMOS image sensor, suitable for low voltage operation, has been developed that implements a built-in dynamic compression function targeted to LinLog behavior, by combining an event based readout of pixels, the use of multiple integrations per frame and the coding of pixel values using the mantissa-exponent principle, to achieve the dynamic range extension