173 research outputs found
Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures
Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy consumption, less noise and EMI emission, and easy design reuse are some of the benefits of these circuits. NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms that has been shown to be a promising method for designing delay-insensitive asynchronous circuits.
This dissertation investigates new areas in NCL design and test and is made of three sections. The first section discusses different CMOS implementations of NCL gates and proposes new circuit techniques to enhance their operation. The second section focuses on mapping multi-rail logic expressions to a standard NCL gate library, which is a form of technology mapping for a category of NCL design automation flows. Finally, the last section proposes design for testability techniques for a recently developed low-power variant of NCL called Sleep Convention Logic (SCL)
Mixed radix design flow for security applications
The purpose of secure devices, such as smartcards, is to protect sensitive information against software and hardware attacks. Implementation of the appropriate protection techniques often implies non-standard methods that are not supported by the conventional design tools. In the recent decade the designers of secure devices have been working hard on customising the workflow. The presented research aims at collecting the up-to-date experiences in this area and create a generic approach to the secure design flow that can be used as guidance by engineers. Well-known countermeasures to hardware attacks imply the use of specific signal encodings. Therefore, multi-valued logic has been considered as a primary aspect of the secure design. The choice of radix is crucial for multi-valued logic synthesis. Practical examples reveal that it is not always possible to find the optimal radix when taking into account actual physical parameters of multi-valued operations. In other words, each radix has its advantages and disadvantages. Our proposal is to synthesise logic in different radices, so it could benefit from their combination. With respect to the design opportunities of the existing tools and the possibilities of developing new tools that would fill the gaps in the flow, two distinct design approaches have been formed: conversion driven design and pre-synthesis. The conversion driven design approach takes the outputs of mature and time-proven electronic design automation (EDA) synthesis tools to generate mixed radix datapath circuits in an endeavour to investigate the added relative advantages or disadvantages. An algorithm underpinning the approach is presented and formally described together with secure gate-level implementations. The obtained results are reported showing an increase in power consumption, thus giving further motivation for the second approach. The pre-synthesis approach is aimed at improving the efficiency by using multivalued logic synthesis techniques to produce an abstract component-level circuit before mapping it into technology libary. Reed-Muller expansions over Galois field arithmetic have been chosen as a theoretical foundation for this approach. In order to enable the combination of radices at the mathematical level, the multi-valued Reed-Muller expansions have been developed into mixed radix Reed-Muller expansions. The goals of the work is to estimate the potential of the new approach and to analyse its impact on circuit parameters down to the level of physical gates. The benchmark results show the approach extends the search space for optimisation and provides information on how the implemented functions are related to different radices. The theory of two-level radix models and corresponding computation methods are the primary theoretical contribution. It has been implemented in RMMixed tool and interfaced to the standard EDA tools to form a complete security-aware design flow.EThOS - Electronic Theses Online ServiceEPSRCGBUnited Kingdo
Analog and Mixed Signal Design towards a Miniaturized Sleep Apnea Monitoring Device
Sleep apnea is a sleep-induced breathing disorder with symptoms of momentary and often repetitive cessations in breathing rhythm or sustained reductions in breathing amplitude. The phenomenon is known to occur with varying degrees of severity in literally millions of people around the world and cause a range of chronicle health issues. In spite of its high prevalence and serious consequences, nearly 80% of people with sleep apnea condition remain undiagnosed. The current standard diagnosis technique, termed polysomnography or PSG, requires the patient to schedule and undergo a complex full-night sleep study in a specially-equipped sleep lab. Due to both high cost and substantial inconvenience, millions of apnea patients are still undiagnosed and thus untreated. This research work aims at a simple, reliable, and miniaturized solution for in-home sleep apnea
diagnosis purposes. The proposed solution bears high-level integration and minimal interference with sleeping patients, allowing them to monitor their apnea conditions at the comfort of their homes.
Based on a MEMS sensor and an effective apnea detection algorithm, a low-cost single-channel apnea screening solution is proposed. A custom designed IC chip implements the apnea detection algorithm using time-domain signal processing techniques. The chip performs autonomous apnea detection and scoring based on the patient’s airflow signals detected by the MEMS sensor. Variable sensitivity is enabled to accommodate different breathing signal amplitudes. The IC chip was fabricated in standard 0.5-μm CMOS technology. A prototype device was designed and assembled including a MEMS sensor, the apnea detection IC chip, a PSoC platform, and wireless transceiver for data transmission. The prototype device demonstrates a valuable screening solution with great potential to reach the broader public with undiagnosed apnea conditions.
In a battery-operated miniaturized medical device, an energy-efficient analog-to-digital converter is an integral part linking the analog world of biomedical signals and the digital domain with powerful signal processing capabilities. This dissertation includes the detailed design of a successive approximation register (SAR) ADC for ultra-low power applications. The ADC adopts an asynchronous 2b/step scheme that halves both conversion time and DAC/digital circuit’s switching activities to reduce static and dynamic energy consumption. A low-power sleep mode is engaged at the end of all conversion steps during each clock period. The technical contributions of this ADC design include an innovative 2b/step reference scheme based on a hybrid R-2R/C-3C DAC, an interpolation-assisted
time-domain 2b comparison scheme, and a TDC with dual-edge-comparison mechanism. The prototype ADC was fabricated in 0.18μm CMOS process with an active area of 0.103 mm^(2), and achieves an ENoB of 9.2 bits and an FoM of 6.7 fJ/conversion-step at 100-kS/s
Memristor-based design solutions for mitigating parametric variations in IoT applications
PhD ThesisRapid advancement of the internet of things (IoT) is predicated by two important factors
of the electronic technology, namely device size and energy-efficiency. With smaller
size comes the problem of process, voltage and temperature (PVT) variations of delays
which are the key operational parameters of devices. Parametric variability is also
an obstacle on the way to allowing devices to work in systems with unpredictable
power sources, such as those powered by energy-harvesters. Designers tackle these
problems holistically by developing new techniques such as asynchronous logic, where
mechanisms such as matching delays are widely used to adapt to delay variations. To
mitigate energy efficiency and power interruption issues the matching delays need to
be ideally retained in a non-volatile storage. Meanwhile, a resistive memory called
memristor becomes a promising component for power-restricted applications owing to
its inherent non-volatility. While providing non-volatility, the use of memristor in delay
matching incurs some power overheads. This creates the first challenge on the way of
introducing memristors into IoT devices for the delay matching.
Another important factor affecting the use of memristors in IoT devices is the
dependence of the memristor value on temperature. For example, a memristance
decoder used in the memristor-based components must be able to correct the read data
without incurring significant overheads on the overall system. This creates the second
challenge for overcoming the temperature effect in memristance decoding process.
In this research, we propose methods for improving PVT tolerance and energy
characteristics of IoT devices from the perspective of above two main challenges:
(i) utilising memristor to enhance the energy efficiency of the delay element (DE), and
(ii) improving the temperature awareness and energy robustness of the memristance
decoder.
For memristor-based delay element (MemDE), we applied a memristor between two
inverters to vary the path resistance, which determines the RC delay. This allows power
saving due to the low number of switching components and the absence of external delay
storage. We also investigate a solution for avoiding the unintended tuning (UT) and a
timing model to estimate the proper pulse width for memristance tuning. The simulation
results based on UMC 180nm technology and VTEAM model show the MemDE can
provide the delay between 0.55ns and 1.44ns which is compatible to the 4-bit multiplexerbased
delay element (MuxDE) in the same technology while consuming thirteen times
less power. The key contribution within (i) is the development of low-power MemDE to
mitigate the timing mismatch caused by PVT variations.
To estimate the temperature effect on memristance, we develop an empirical temperature
model which fits both titanium dioxide and silver chalcogenide memristors. The
temperature experiments are conducted using the latter device, and the results confirm
the validity of the proposed model with the accuracy R-squared >88%. The memristance
decoder is designed to deliver two key advantages. Firstly, the temperature model is
integrated into the VTEAM model to enable the temperature compensation. Secondly, it
supports resolution scalability to match the energy budget. The simulation results of the
2-bit decoder based on UMC 65nm technology show the energy can be varied between
49fJ and 98fJ. This is the second major contribution to address the challenge (ii).
This thesis gives future research directions into an in-depth study of the memristive
electronics as a variation-robust energy-efficient design paradigm and its impact on
developing future IoT applications.sponsored by the Royal Thai Governmen
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