INFOPLEX : hierarchical decomposition of a large information management system using a microprocessor complex

Bibliography: leaves 20-22.Stuart E. Madnick

Dynamic reordering of high latency transactions in time-warp simulation using a modified micropipeline

technical reportTime warp based simulation of discrete-event systems is an efficient way to overcome the synchronization overhead during distributed simulation. As computations may proceed beyond synchronization barriers in time warp, multiple checkpoints of state need to be maintained to be able to rollback invalidated branches of the lookahead execution. An efficient mechanism to implement state rollback has been proposed in [IEEE Transactions on Computers, January 1992]. In this environment, a dedicated Roll-back Chip (RBC) maintains multiple versions of state by responding to a set of control instructions interspersed with the regular stream of data-access instructions. As these control instructions have latencies that are orders of magnitude more than the latencies of data-access instructions, a strict ordering of the instructions may lead to large inefficiencies. This paper describes a dynamic instruction reordering scheme that optimizes multiple pending instructions to achieve higher throughput. A modified asynchronous micropipeline, called the Asynchronous Reorder Pipeline (ARP) has been chosen to implement this scheme. ARP can be easily adapted for supporting dynamic instruction reordering in other situations also. After outlining the design of the ARP, we present its high level protocol, and a correctness argument. We then present two new primitive asynchronous components that are used in the ARP: a lockable C-element LockC, and an exchange pipeline stage ExLatch. Circuit level simulation results are presented to justify that LockC - a critical component of our design - functions correctly. The newly proposed primitives, as well as the ARP itself, are useful in other contexts as well

C-MOS array design techniques: SUMC multiprocessor system study

The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units

Integrated shared-memory and message-passing communication in the Alewife multiprocessor

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 237-246) and index.by John David Kubiatowicz.Ph.D

Submicron Systems Architecture: Semiannual Technical Report

No abstract available

N-Dimensional Perfect Pipelining

In this paper, we introduce a technique to parallelize nested loops at the fine grain level. It is a generalization of Perfect Pipelining which was developed to parallelize a single-nested loop at the fine grain level. Previous techniques that can parallelize nested loops, e.g. DOACROSS or Wavefront method, mostly belong to the coarse grain approach. We explain our method, contrast it with the coarse grain techniques, and show the benefits of parallelizing nested loops at the fine grain level