64,725 research outputs found
The SystemJ approach to system-level design
In this paper, we propose a new system-level design language, called SystemJ. It extends Java with synchronous reactive features present in Esterel and asynchronous constructs suitable for modelling globally asynchronous locally synchronous systems. The strength of SystemJ comes from its ability to offer the data processing and encapsulation elegance of Java, Esterel-like reactivity and synchrony, and the asynchronous de-coupling of CSP all within the Java framework. Using standard Java environments, for specification and modelling, or specialised reactive embedded processors, for high performance implementation, the SystemJ design flow is extremely versatile. With the increasing attention that Java gets in embedded systems, SystemJ comes to address data and control, software and hardware, modelling and implementation in a unified manner
Augmenting High-Level Petri Nets to Support GALS Distributed Embedded Systems Specification
Part 9: Embedded Systems and Petri NetsInternational audienceHigh-level Petri net classes are suited to specify concurrent processes with emphasis both in control and data processing, making them appropriate to specify distributed embedded systems (DES). Embedded systems components are usually synchronous, which means that DES can be seen as Globally-Asynchronous Locally-Synchronous (GALS) systems. This paper proposes to include in high-level Petri nets a set of concepts already introduced for low-level Petri nets allowing the specification of GALS systems, namely time domains, test arcs and priorities. Additionally, this paper proposes external messages and three types of (high-level) asynchronous communication channels, to specify the interaction between distributed components based on message exchange. With these extensions, GALS-DES can be specified using high-level Petri nets. The resulting models include the specification of each component with well-defined boundaries and interface, and also the explicit specification of the asynchronous interaction between components. These models will be used not only to specify the system behavior, but also to be the input for model-checking tools (supporting its verification) and automatic code generation tools (supporting its implementation in software and hardware platforms), giving a contribution to the model-based development approach and hardware-software co-design of DES based on high-level Petri nets
Centralized vs distributed communication scheme on switched ethernet for embedded military applications
Current military communication network is a generation
old and is no longer effective in meeting the emerging
requirements imposed by the future embedded military applications. Therefore, a new interconnection system is needed to overcome these limitations. Two new communication networks based upon Full Duplex Switched Ethernet are presented herein in this aim. The first one uses a distributed communication scheme where equipments can emit their data simultaneously, which clearly improves system’s throughput and flexibility. However, migrating all existing applications into a compliant form could be an expensive step. To avoid this process, the second proposal consists in keeping the current centralized communication scheme. Our objective is to assess and compare the real time
guarantees that each proposal can offer. The paper includes the functional description of each proposed communication network and a military avionic application to highlight proposals ability to support the required time constrained communications
Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review
The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER
Performance analysis of a Master/Slave switched Ethernet for military embedded applications
Current military communication network is a generation
old and is no longer effective in meeting the emerging
requirements imposed by the next generation military embedded applications. A new communication network based upon Full Duplex Switched Ethernet is proposed in this paper to overcome these limitations. To allow existing military subsystems to be easily supported by a Switched Ethernet network, our proposal consists in keeping their current centralized communication scheme by using an optimized master/slave transmission control on Switched Ethernet thanks to the Flexible Time Triggered (FTT) paradigm. Our main objective is to assess the performance
of such a proposal and estimate the quality of service we
can expect in terms of latency. Using the Network Calculus formalism, schedulability analysis are determined. These analysis are illustrated in the case of a realistic military embedded application extracted from a real military aircraft network, to highlight the proposal's ability to support the required time constrained communications
Embedding Multi-Task Address-Event- Representation Computation
Address-Event-Representation, AER, is a communication protocol that is
intended to transfer neuronal spikes between bioinspired chips. There are
several AER tools to help to develop and test AER based systems, which may
consist of a hierarchical structure with several chips that transmit spikes
among them in real-time, while performing some processing. Although these
tools reach very high bandwidth at the AER communication level, they require
the use of a personal computer to allow the higher level processing of the
event information. We propose the use of an embedded platform based on a
multi-task operating system to allow both, the AER communication and
processing without the requirement of either a laptop or a computer. In this
paper, we present and study the performance of an embedded multi-task AER
tool, connecting and programming it for processing Address-Event
information from a spiking generator.Ministerio de Ciencia e Innovación TEC2006-11730-C03-0
Evaluating XMPP Communication in IEC 61499-based Distributed Energy Applications
The IEC 61499 reference model provides an international standard developed
specifically for supporting the creation of distributed event-based automation
systems. Functionality is abstracted into function blocks which can be coded
graphically as well as via a text-based method. As one of the design goals was
the ability to support distributed control applications, communication plays a
central role in the IEC 61499 specification. In order to enable the deployment
of functionality to distributed platforms, these platforms need to exchange
data in a variety of protocols. IEC 61499 realizes the support of these
protocols via "Service Interface Function Blocks" (SIFBs). In the context of
smart grids and energy applications, IEC 61499 could play an important role, as
these applications require coordinating several distributed control logics.
Yet, the support of grid-related protocols is a pre-condition for a wide-spread
utilization of IEC 61499. The eXtensible Messaging and Presence Protocol (XMPP)
on the other hand is a well-established protocol for messaging, which has
recently been adopted for smart grid communication. Thus, SIFBs for XMPP
facilitate distributed control applications, which use XMPP for exchanging all
control relevant data, being realized with the help of IEC 61499. This paper
introduces the idea of integrating XMPP into SIFBs, demonstrates the
prototypical implementation in an open source IEC 61499 platform and provides
an evaluation of the feasibility of the result.Comment: 2016 IEEE 21st International Conference on Emerging Technologies and
Factory Automation (ETFA
Adaptive Duty Cycling MAC Protocols Using Closed-Loop Control for Wireless Sensor Networks
The fundamental design goal of wireless sensor MAC protocols is to minimize unnecessary power consumption of the sensor nodes, because of its stringent resource constraints and ultra-power limitation. In existing MAC protocols in wireless sensor networks (WSNs), duty cycling, in which each node periodically cycles between the active and sleep states, has been introduced to reduce unnecessary energy consumption. Existing MAC schemes, however, use a fixed duty cycling regardless of multi-hop communication and traffic fluctuations. On the other hand, there is a tradeoff between energy efficiency and delay caused by duty cycling mechanism in multi-hop communication and existing MAC approaches only tend to improve energy efficiency with sacrificing data delivery delay. In this paper, we propose two different MAC schemes (ADS-MAC and ELA-MAC) using closed-loop control in order to achieve both energy savings and minimal delay in wireless sensor networks. The two proposed MAC schemes, which are synchronous and asynchronous approaches, respectively, utilize an adaptive timer and a successive preload frame with closed-loop control for adaptive duty cycling. As a result, the analysis and the simulation results show that our schemes outperform existing schemes in terms of energy efficiency and delivery delay
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