7 research outputs found
A system for calculating the greatest common denominator implemented using asynchrobatic logic
An asynchrobatic system that uses Euclid's algorithm to calculate the greatest common denominator of two numbers is presented. This algorithm is a simple system that contains both repetition and decision, and therefore demonstrates that asynchrobatic logic can be used to implement arbitrarily complex computational systems. Under typical conditions on a 0.35 mum process, a 16-bit implementation can perform a 24-cycle test vector in 2.067 mus with a power consumption of 3.257 nW
An asynchrobatic, radix-four, carry look-ahead adder
A low-power, Asynchrobatic (asynchronous, quasi-adiabatic), sixteen-bit, radix-four, parallel-prefix adder circuit is presented. The results show that it is an efficient, low power design, and that as would be expected with an asynchronous design, its performance is determined by its operating conditions. On a 0.35 mum CMOS process, under ldquotypicalrdquo process conditions, operating at an effective frequency of 22 MHz, an addition can be performed using 69 pW, with 48.3 pW used by the control logic and 20.7 pW by the data-path
Asynchrobatic logic for low-power VLSI design
In this work, Asynchrobatic Logic is presented. It is a novel low-power
design style that combines the energy saving benefits of asynchronous logic
and adiabatic logic to produce systems whose power dissipation is reduced in
several different ways. The term “Asynchrobatic” is a new word that can be
used to describe these types of systems, and is derived from the
concatenation and shortening of Asynchronous, Adiabatic Logic. This thesis
introduces the concept and theory behind Asynchrobatic Logic. It first
provides an introductory background to both underlying parent technologies
(asynchronous logic and adiabatic logic). The background material continues
with an explanation of a number of possible methods for designing complex
data-path cells used in the adiabatic data-path. Asynchrobatic Logic is then
introduced as a comparison between asynchronous and Asynchrobatic buffer
chains, showing that for wide systems, it operates more efficiently. Two
more-complex sub-systems are presented, firstly a layout implementation of
the substitution boxes from the Twofish encryption algorithm, and secondly a
front-end only (without parasitic capacitances, resistances) simulation that
demonstrates a functional system capable of calculating the Greatest
Common Denominator (GCD) of a pair of 16-bit unsigned integers, which
under typical conditions on a 0.35μm process, executed a test vector requiring
twenty-four iterations in 2.067μs with a power consumption of 3.257nW.
These examples show that the concept of Asynchrobatic Logic has the
potential to be used in real-world applications, and is not just theory without
application. At the time of its first publication in 2004, Asynchrobatic Logic
was both unique and ground-breaking, as this was the first time that
consideration had been given to operating large-scale adiabatic logic in an
asynchronous fashion, and the first time that Asynchronous Stepwise
Charging (ASWC) had been used to drive an adiabatic data-path
Using positive feedback adiabatic logic to implement reversible Toffoli gates
A reversible, positive feedback adiabatic logic circuit is presented, which by implementing the universal Toffoli gate demonstrates that reversible logic circuits can be created and implemented using this adiabatic logic family. When compared to circuits with similar circuit structures that do not incorporate complete recovery logic, the use of reversible structures shows a reduction in energy losses by a mean of just under 63%
Investigation of Stepwise Charging Circuits for Power-Clock Generation in Adiabatic Logic
The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider stepwise charging strategies (2, 3, 4, 5, 6, 7, and 8-step) based on tank-capacitor circuits, comparing them in terms of their energy recovery properties and complexity. We show that energy recovery achievable depends on the tank-capacitor size. We also show that tank-capacitor sizes can be reduced as their number increases concluding that combined tank capacitance (CTT) versus load capacitance (CL) ratio is the significant parameter. We propose that using a CTT/CL ratio of 10 and using a 4-step charging power-clock constitute appropriate trade-offs in practical circuits
Adiabatic Approach for Low-Power Passive Near Field Communication Systems
This thesis tackles the need of ultra-low power electronics in the power limited passive Near Field Communication (NFC) systems. One of the techniques that has proven the potential of delivering low power operation is the Adiabatic Logic Technique. However, the low power benefits of the adiabatic circuits come with the challenges due to the absence of single opinion on the most energy efficient adiabatic logic family which constitute appropriate trade-offs between computation time, area and complexity based on the circuit and the power-clocking schemes. Therefore, five energy efficient adiabatic logic families working in single-phase, 2-phase and 4-phase power-clocking schemes were chosen.
Since flip-flops are the basic building blocks of any sequential circuit and the existing flip-flops are MUX-based (having more transistors) design, therefore a novel single-phase, 2-phase and 4-phase reset based flip-flops were proposed. The performance of the multi-phase adiabatic families was evaluated and compared based on the design examples such as 2-bit ring counter, 3-bit Up-Down counter and 16-bit Cyclic Redundancy Check (CRC) circuit (benchmark circuit) based on ISO 14443-3A standard. Several trade-offs, design rules, and an appropriate range for the supply voltage scaling for multi-phase adiabatic logic are proposed.
Furthermore, based on the NFC standard (ISO 14443-3A), data is frequently encoded using Manchester coding technique before transmitting it to the reader. Therefore, if Manchester encoding can be implemented using adiabatic logic technique, energy benefits are expected. However, adiabatic implementation of Manchester encoding presents a challenge. Therefore, a novel method for implementing Manchester encoding using adiabatic logic is proposed overcoming the challenges arising due to the AC power-clock.
Other challenges that come with the dynamic nature of the adiabatic gates and the complexity of the 4-phase power-clocking scheme is in synchronizing the power-clock v
phases and the time spent in designing, validation and debugging of errors. This requires a specific modelling approach to describe the adiabatic logic behaviour at the higher level of abstraction. However, describing adiabatic logic behaviour using Hardware Description Languages (HDLs) is a challenging problem due to the requirement of modelling the AC power-clock and the dual-rail inputs and outputs. Therefore, a VHDL-based modelling approach for the 4-phase adiabatic logic technique is developed for functional simulation, precise timing analysis and as an improvement over the previously described approaches
Robustness and durability aspects in the design of power management circuits for IoT applications
With the increasing interest in the heterogeneous world of the “Internet of Things” (IoT), new compelling challenges arise in the field of electronic design, especially concerning the development of innovative power management solutions. Being this diffusion a consolidated reality nowadays, emerging needs like lifetime, durability and robustness are becoming the new watchwords for power management, being a common ground which can dramatically improve service life and confidence in these devices. The possibility to design nodes which do not need external power supply is a crucial point in this scenario. Moreover, the development of autonomous nodes which are substantially maintenance free, and which therefore can be placed in unreachable or harsh environments is another enabling aspect for the exploitation of this technology. In this respect, the study of energy harvesting techniques is increasingly earning interest again.
Along with efficiency aspects, degradation aspects are the other main research field with respect to lifetime, durability and robustness of IoT devices, especially related to aging mechanisms which are peculiar in power management and power conversion circuits, like for example battery wear during usage or hot-carrier degradation (HCD) in power MOSFETs. In this thesis different aspects related to lifetime, durability and robustness in the field of power management circuits are studied, leading to interesting contributions. Innovative designs of DC/DC power converters are studied and developed, especially related to reliability aspects of the use of electrochemical cells as power sources. Moreover, an advanced IoT node is proposed, based on energy harvesting techniques, which features an intelligent dynamically adaptive power management circuit. As a further contribution, a novel algorithm is proposed, which is able to effectively estimate the efficiency of a DC/DC converter for photovoltaic applications at runtime. Finally, an innovative DC/DC power converter with embedded monitoring of hot-carrier degradation in power MOSFETs is designed