2,327 research outputs found

    Ultra-Low Power Circuit Design for Cubic-Millimeter Wireless Sensor Platform.

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    Modern daily life is surrounded by smaller and smaller computing devices. As Bell’s Law predicts, the research community is now looking at tiny computing platforms and mm3-scale sensor systems are drawing an increasing amount of attention since they can create a whole new computing environment. Designing mm3-scale sensor nodes raises various circuit and system level challenges and we have addressed and proposed novel solutions for many of these challenges to create the first complete 1.0mm3 sensor system including a commercial microprocessor. We demonstrate a 1.0mm3 form factor sensor whose modular die-stacked structure allows maximum volume utilization. Low power I2C communication enables inter-layer serial communication without losing compatibility to standard I2C communication protocol. A dual microprocessor enables concurrent computation for the sensor node control and measurement data processing. A multi-modal power management unit allowed energy harvesting from various harvesting sources. An optical communication scheme is provided for initial programming, synchronization and re-programming after recovery from battery discharge. Standby power reduction techniques are investigated and a super cut-off power gating scheme with an ultra-low power charge pump reduces the standby power of logic circuits by 2-19× and memory by 30%. Different approaches for designing low-power memory for mm3-scale sensor nodes are also presented in this work. A dual threshold voltage gain cell eDRAM design achieves the lowest eDRAM retention power and a 7T SRAM design based on hetero-junction tunneling transistors reduces the standby power of SRAM by 9-19× with only 15% area overhead. We have paid special attention to the timer for the mm3-scale sensor systems and propose a multi-stage gate-leakage-based timer to limit the standard deviation of the error in hourly measurement to 196ms and a temperature compensation scheme reduces temperature dependency to 31ppm/°C. These techniques for designing ultra-low power circuits for a mm3-scale sensor enable implementation of a 1.0mm3 sensor node, which can be used as a skeleton for future micro-sensor systems in variety of applications. These microsystems imply the continuation of the Bell’s Law, which also predicts the massive deployment of mm3-scale computing systems and emergence of even smaller and more powerful computing systems in the near future.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91438/1/sori_1.pd

    Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

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    Embedded memories were once utilized to transfer information between the CPU and the main memory. The cache storage in most traditional computers was static-random-access-memory (SRAM). Other memory technologies, such as embedded dynamic random-access memory (eDRAM) and spin-transfer-torque random-access memory (STT-RAM), have also been used to store cache data. The SRAM, on the other hand, has a low density and severe leakage issues, and the STT-RAM has high latency and energy consumption when writing. The gain-cell eDRAM (GC-eDRAM), which has a higher density, lower leakage, logic compatibility, and is appropriate for two-port operations, is an attractive option. To speed up data retrieval from the main memory, future processors will require larger and faster-embedded memories. Area overhead, power overhead, and speed performance are all issues with the existing architecture. A unique mixed-V_T 3T GC-eDRAM architecture is suggested in this paper to improve data retention times (DRT) and performance for better energy efficiency in embedded memories. The GC-eDRAM is simulated using a standard complementary-metal-oxide-semiconductor (CMOS) with a 130nm technology node transistor. The performance of a 2kbit mixed-V_T 3T GC-eDRAM array were evaluated through corner process simulations. Each memory block is designed and simulated using Mentor Graphics Software. The array, which is based on the suggested bit-cell, has been successfully operated at 400Mhz under a 1V supply and takes up almost 60-75% less space than 6T SRAM using the same technology. When compared to the existing 6T and 4T ULP SRAMs (others' work), the retention power of the proposed GC-eDRAM is around 80-90% lower

    All-optical Semiconductor Optical Amplifiers Using Quantum Dots (Optical Pumping)

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    In the first portion of this chapter, a short review on all-optical processing is presented. Following the ideas of all-optical processing, a basic unit cell is introduced for the realization of these systems. To this end, an all-optical semiconductor optical amplifier based on quantum dots (QD-SOA) is presented and used as the basic unit cell. Then, a novel scheme for a high-speed all-optical half-adder based on quantum dot semiconductor optical amplifiers has been theoretically and extensively analyzed. We accelerate the gain recovery process in QD-SOA with a control pulse (CP) using the cross-gain modulation (XGM) effect in QD-SOA (based on a novel work reported by Rostami et al published in IEEE J. Quantum Electron in 2010). In this proposed scheme, a pair of input data streams simultaneously drives the switch to produce sum and carry. The proposed scheme is driven by the pair of input data streasms for one switch between which the Boolean XOR function is to be executed to produce a sum-bit. Then, one of the input data is utilized to drive the second switch and another is used as input data for it to produce a carry-bit. In the proposed structure, we need to use an optical attenuator to reduce the power level of the optical signal. Thee, data pulse is at least an order of magnitude stronger than the incoming pulse; thereforehowever, only the input pulse can alter QD-SOA’s optical properties. Also, an all-optical cross-phase modulation (XPM) wavelength converter has been utilized to obtain an all-optical AND gate, which is logic CARRY. Logic SUM and CARRY are simultaneously realized in the proposed structure. The operation of the system is evaluated and demonstrated with a Tb/s bit rate. The proposed structure is mathematically modeled by writing rate equations and then is numerically simulated with success. High-speed operation capabilities of the proposed all-optical half-adder structure are evaluated by numerical simulation

    CAMAC bulletin: A publication of the ESONE Committee Issue #3 March 1972

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    CAMAC is a means of interconnecting many peripheral devices through a digital data highway to a data processing device such as a computer

    Design of Logic-Compatible Embedded Flash Memories for Moderate Density On-Chip Non-Volatile Memory Applications

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    University of Minnesota Ph.D. dissertation. December 2013. Major: Electrical Engineering. Advisor: Chris H. Kim. 1 computer file (PDF); xx, 129 pages.An on-chip embedded NVM (eNVM) enables a zero-standby power system-on-a-chip with a smaller form factor, faster access speed, lower access power, and higher security than an off-chip NVM. Differently from the high density eNVM technologies such as dual-poly eflash, FeRAM, STT-MRAM, and RRAM that typically require process overhead beyond standard logic process, the moderate density eNVM technologies such as e-fuse, anti-fuse, and single-poly embedded flash (eflash) can be fabricated in a standard logic process with no process overhead. Among them, a single-poly eflash is a unique multiple-time programmable moderate density eNVM, while it is expected to play a key role in mitigating variability and reliability issues of the future VLSI technologies; however, the challenges such as a high voltage disturbance, an implementation of logic compatible High Voltage Switch (HVS), and a limited sensing margin are required to be solved for its implementation using a standard I/O device. This thesis focuses on alleviating such challenges of the single-poly eflash memory with three single-poly eflash designs proposed in a generic logic process for moderate density eNVM applications. Firstly, the proposed 5T eflash features a WL-by-WL accessible architecture with no disturbance issue of the unselected WL cells, an overstress-free multi-story HVS expanding the cell sensing margin, and a selective WL refresh scheme for the higher cell endurance. The most favorable eflash cell configuration is also studied when the performance, endurance, retention, and disturbance characteristics are all considered. Secondly, the proposed 6T eflash features the bit-by-bit re-write capability for the higher overall cell endurance, while not disturbing the unselected WL cells. The logic compatible on-chip charge pump to provide the appropriate high voltages for the proposed eflash operations is also discussed. Finally, the proposed 10T eflash features a multi-configurable HVS that does not require the boosted read supplies, and a differential cell architecture with improved retention time. All these proposed eflash memories were implemented in a 65nm standard logic process, and the test chip measurement results confirmed the functionality of the proposed designs with a reasonable retention margin, showing the competitiveness of the proposed eflash memories compared to the other moderate density eNVM candidates

    Large scale modeling, model reduction and control design for a real-time mechatronic system

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    Mechatronics is the synergistic integration of the techniques from mechanical engineering, electrical engineering and information technology, which influences each other mutually. As a multidisciplinary domain, mechatronics is more than mechanical or electronics, and the mechatronic systems are always composed of a number of subsystems with various controllers. From this point of view, a lot of such systems can be defined as large scale system. The key element of such systems is integration. Modeling of mechatronic system is a very important step in developing control design of such products, so as to simulate and analyze their dynamic responses for control design, making sure they would meet the desired requirements. The models of large scale systems are always resulted in complex form and high in dimension, making the computation for modeling, simulation and control design become very complicated, or even beyond the solutions provided by conventional engineering methods. Therefore, a simplified model obtained by using model order reduction technique, which can preserve the dominant physical parameters and reveal the performance limiting factor, is preferred. In this dissertation, the research have chosen the two-wheeled self-balancing scooter as the subject of the study in research on large scale mechatronic system, and efforts have been put on developing a completed mathematical modeling method based on a unified framework from varitional method for both mechanical subsystem and electrical subsystem in the scooter. In order to decrease the computation efforts in simulation and control design, Routh model reduction technique was chosen from various model reduction techniques so as to obtain a low dimensional model. Matlab simulation is used to predict the system response based on the simplified model and related control design. Furthermore, the final design parameters were applied in the physical system of two-wheeled self-balancing scooter to test the real performance so as to finish the design evaluation. Conclusion was made based on these results and further research directions can be predicte

    Theoretical Engineering and Satellite Comlink of a PTVD-SHAM System

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    This paper focuses on super helical memory system's design, 'Engineering, Architectural and Satellite Communications' as a theoretical approach of an invention-model to 'store time-data'. The current release entails three concepts: 1- an in-depth theoretical physics engineering of the chip including its, 2- architectural concept based on VLSI methods, and 3- the time-data versus data-time algorithm. The 'Parallel Time Varying & Data Super-helical Access Memory' (PTVD-SHAM), possesses a waterfall effect in its architecture dealing with the process of voltage output-switch into diverse logic and quantum states described as 'Boolean logic & image-logic', respectively. Quantum dot computational methods are explained by utilizing coiled carbon nanotubes (CCNTs) and CNT field effect transistors (CNFETs) in the chip's architecture. Quantum confinement, categorized quantum well substrate, and B-field flux involvements are discussed in theory. Multi-access of coherent sequences of 'qubit addressing' in any magnitude, gained as pre-defined, here e.g., the 'big O notation' asymptotically confined into singularity while possessing a magnitude of 'infinity' for the orientation of array displacement. Gaussian curvature of k(k<0) is debated in aim of specifying the 2D electron gas characteristics, data storage system for defining short and long time cycles for different CCNT diameters where space-time continuum is folded by chance for the particle. Precise pre/post data timing for, e.g., seismic waves before earthquake mantle-reach event occurrence, including time varying self-clocking devices in diverse geographic locations for radar systems is illustrated in the Subsections of the paper. The theoretical fabrication process, electromigration between chip's components is discussed as well.Comment: 50 pages, 10 figures (3 multi-figures), 2 tables. v.1: 1 postulate entailing hypothetical ideas, design and model on future technological advances of PTVD-SHAM. The results of the previous paper [arXiv:0707.1151v6], are extended in order to prove some introductory conjectures in theoretical engineering advanced to architectural analysi

    VLSI Design

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    This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

    The Deep Space Network

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    The objectives, functions, and organization of the Deep Space Network are summarized. The Deep Space Instrumentation Facility, the Ground Communications Facility, and the Network Control System are described
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