A framework for system level verification : the SystemC Case

Recent advances in hardware design has enabled integration of a complete yet complex systems on a single chip (called System-on-a-Chip: SoC). It is conceivable that the role of traditional Register Transfer level (RTL) languages will diminish to an extent akin to assembly level languages in software design. Therefore, new design languages or so-called System Level Languages (SLL) have emerged. Verification techniques for SOC designs also need to change with this trend. Combining classical verification techniques, such as simulation, with several other formal techniques, into a single approach has been gaining attention in SoC verification. Classical simulation based verification techniques when used with SystemC face several problems related to the object-oriented aspect of SystemClibrary and due to the complexity of its simulation environment. In this talk, we present our proposed methodology to verify SoC designs modeled in SystemC. To this end, we introduce a hybrid approach combining static code analysis, model checking and assertion based verification. We also propose to augment the approach by a test generation module in order to improve the coverage metrics in comparison to the classical simulation approach (mainly based on random test generation

A TLM-RTL Systemverilog-Based Verification Franework for OCP Design

Open Core Protocol (OCP) establishes itself as the only non-proprietary, openly licensed, core-centric protocol that is used to support “plug-and-play” SoC (System-On-Chip) design practices. Designer can reuse OCP-compliance IP cores based on system integration and verification approach in multiple designs without reworking, reducing the development time and cutting down overall design costs. In this thesis, we develop a reusable verification framework of OCP. Assertion-based verification was chosen in order to enforce the flow. An OCP SystemVerilog monitor which is developed in house is used to verify the OCP SystemC TL1 (Cycle-accurate Level) design. The monitor can also be reused for OCP designs described at different abstraction level and thus dramatically reduce the time needed for OCP functional verification. To increase the functional coverage of OCP models, Cell-based Genetic Algorithm (CGA) with random number generators based on different probability distribution functions is provided on OCP TL1 models for generating and evolving the OCP transactions. Furthermore, SystemC Verification Library (SCV) is employed as pure random number generator to compare with the proposed CGA. The experiments show that some probability distributions have more effect on the coverage than others. The best population of the CGA can be reused on OCP RTL models to reduce the verification time

Analog Property Checkers: A Ddr2 Case Study

The formal specification component of verification can be exported to simulation through the idea of property checkers. The essence of this approach is the automatic construction of an observer from the specification in the form of a program that can be interfaced with a simulator and alert the user if the property is violated by a simulation trace. Although not complete, this lighter approach to formal verification has been effectively used in software and digital hardware to detect errors. Recently, the idea of property checkers has been extended to analog and mixed-signal systems. In this paper, we apply the property-based checking methodology to an industrial and realistic example of a DDR2 memory interface. The properties describing the DDR2 analog behavior are expressed in the formal specification language stl/psl in form of assertions. The simulation traces generated from an actual DDR2 interface design are checked with respect to the stl/psl assertions using the amt tool. The focus of this paper is on the translation of the official (informal and descriptive) specification of two non-trivial DDR2 properties into stl/psl assertions. We study both the benefits and the current limits of such approach

A Historical Perspective on Runtime Assertion Checking in Software Development

This report presents initial results in the area of software testing and analysis produced as part of the Software Engineering Impact Project. The report describes the historical development of runtime assertion checking, including a description of the origins of and significant features associated with assertion checking mechanisms, and initial findings about current industrial use. A future report will provide a more comprehensive assessment of development practice, for which we invite readers of this report to contribute information