Performance of Transmit Antenna Selection in Multiple Input Multiple Output-Orthogonal Space Time Block Code (MIMO-OSTBC) System Joint with Bose-Chaudhuri-Hocquenghem (BCH)-Turbo Code (TC) in Rayleigh Fading Channel

To enhancing the performance of spatial modulation (SM) systems TAS (Transmit antenna selection) technique need to be essential. This TAS is an effective technique for reducing the Multiple Input Multiple Output (MIMO) systems computational difficulty and Bit error rate (BER) can increase remarkably by various TAS algorithms. But these selection methods cannot provide code gain, so it is essential to join the TAS with external code to obtain code gain advantages in BER. In some existing work, the improved BER has been perceived by joining Forward Error Correction Code (FEC) and Space Time Block Code (STBC) for MIMO systems provided greater code gain. A multiple TAS-OSTBC technique with new integration of Bose–Chaudhuri–Hocquenghem (BCH)-Turbo code (TC) is proposed in our paper. With external BCH code in sequence with the inner Turbo code, the TAS-OSTBC system is joining. This combination can provide increasing code gain and the effective advantages of the TAS-OSTBC system. To perform the system analysis Rayleigh channel is utilized. In the case with multiple TAS-OSTBC systems, better performance can provide by this new joint of the BCH-Turbo compared to the conventional Turbo code for the Rayleigh fading

Design of a simulation platform to test next generation of terrestrial DVB

Digital Terrestrial Television Broadcasting (DTTB) is a member of our daily life routine, and nonetheless, according to new users’ necessities in the fields of communications and leisure, new challenges are coming up. Moreover, the current Standard is not able to satisfy all the potential requirements. For that reason, first of all, a review of the current Standard has been performed within this work. Then, it has been identified the needing of developing a new version of the standard, ready to support enhanced services, as for example broadcasting transmissions to moving terminals or High Definition Television (HDTV) transmissions, among others. The main objective of this project is the design and development of a physical layer simulator of the whole DVB-T standard, including both the complete transmission and reception procedures. The simulator has been developed in Matlab. A detailed description of the simulator both from a functional and an architectural point of view is included. The simulator is the base for testing any possible modifications that may be included into the DVB-T2 future standard. In fact, several proposed enhancements have already been carried out and their performance has been evaluated. Specifically, the use of higher order modulation schemes, and the corresponding modifications in all the system blocks, have been included and evaluated. Furthermore, the simulator will allow testing other enhancements as the use of more efficient encoders and interleavers, MIMO technologies, and so on. A complete set of numerical results showing the performance of the different parts of the system, are presented in order to validate the correctness of the implementation and to evaluate both the current standard performance and the proposed enhancements. This work has been performed within the context of a project called FURIA, which is a strategic research project funded by the Spanish Ministry of Industry, Tourism and Commerce. A brief description of this project and its consortium has been also included herein, together with an introduction to the current situation of the DTTB in Spain (called TDT in Spanish)

Design of a simulation platform to test next generation of terrestrial DVB

Digital Terrestrial Television Broadcasting (DTTB) is a member of our daily life routine, and nonetheless, according to new users’ necessities in the fields of communications and leisure, new challenges are coming up. Moreover, the current Standard is not able to satisfy all the potential requirements. For that reason, first of all, a review of the current Standard has been performed within this work. Then, it has been identified the needing of developing a new version of the standard, ready to support enhanced services, as for example broadcasting transmissions to moving terminals or High Definition Television (HDTV) transmissions, among others. The main objective of this project is the design and development of a physical layer simulator of the whole DVB-T standard, including both the complete transmission and reception procedures. The simulator has been developed in Matlab. A detailed description of the simulator both from a functional and an architectural point of view is included. The simulator is the base for testing any possible modifications that may be included into the DVB-T2 future standard. In fact, several proposed enhancements have already been carried out and their performance has been evaluated. Specifically, the use of higher order modulation schemes, and the corresponding modifications in all the system blocks, have been included and evaluated. Furthermore, the simulator will allow testing other enhancements as the use of more efficient encoders and interleavers, MIMO technologies, and so on. A complete set of numerical results showing the performance of the different parts of the system, are presented in order to validate the correctness of the implementation and to evaluate both the current standard performance and the proposed enhancements. This work has been performed within the context of a project called FURIA, which is a strategic research project funded by the Spanish Ministry of Industry, Tourism and Commerce. A brief description of this project and its consortium has been also included herein, together with an introduction to the current situation of the DTTB in Spain (called TDT in Spanish)

Five decades of hierarchical modulation and its benefits in relay-aided networking

Hierarchical modulation (HM), which is also known as layered modulation, has been widely adopted across the telecommunication industry. Its strict backward compatibility with single-layer modems and its low complexity facilitate the seamless upgrading of wireless communication services. The specific features of HM may be conveniently exploited for improving the throughput/information-rate of the system without requiring any extra bandwidth, while its complexity may even be lower than that of the equivalent system relying on conventional modulation schemes. As a recent research trend, the potential employment of HM in the context of cooperative communications has also attracted substantial research interests. Motivated by the lower complexity and higher flexibility of HM, we provide a comprehensive survey and conclude with a range of promising future research directions. Our contribution is the conception of a new cooperative communication paradigm relying on turbo trellis-coded modulation-aided twin-layer HM-16QAM and the analytical performance investigation of a four-node cooperative communication network employing a novel opportunistic routing algorithm. The specific performance characteristics evaluated include the distribution of delay, the outage probability, the transmit power of each node, the average packet power consumption, and the system throughput. The simulation results have demonstrated that when transmitting the packets formed by layered modulated symbol streams, our opportunistic routing algorithm is capable of reducing the transmit power required for each node in the network compared with that of the system using the traditional opportunistic routing algorithm. We have also illustrated that the minimum packet power consumption of our system using our opportunistic routing algorithm is also lower than that of the system using the traditional opportunistic routing algorithm

Irregular Generic Detection Aided Iterative Downlink SDMA Systems

Abstract—When an iterative-decoding aided system is configured to operate at a near-capacity performance, an excessive complexity may be imposed by the iterative process. In this paper, we propose the novel framework of generic detection, which invokes appropriately amalgamated multiple detectors. Hence the proposed Irregular Generic Detection (IrGD) algorithm may reduce the complexity of iterative detectors. We show in the context of an iterative Down-Link (DL) Space Division Multiple Access (SDMA) system that the proposed IrGD may indeed reduce the complexity of the iterative receiver. The IrGD aided DL-SDMA system detects the appropriate fractions of the received bitstream with the aid of different detectors. This allows us to match the Extrinsic Information Transfer (EXIT) curve of the detector to that of the channel decoder, hence facilitating a near-capacity operation, which reducing the detection complexity by about 28% compared to a powerful near-Maximum-Likelihood (ML) sphere detector benchmark system

A STUDY OF ERASURE CORRECTING CODES

This work focus on erasure codes, particularly those that of high performance, and the related decoding algorithms, especially with low computational complexity. The work is composed of different pieces, but the main components are developed within the following two main themes. Ideas of message passing are applied to solve the erasures after the transmission. Efficient matrix-representation of the belief propagation (BP) decoding algorithm on the BEG is introduced as the recovery algorithm. Gallager's bit-flipping algorithm are further developed into the guess and multi-guess algorithms especially for the application to recover the unsolved erasures after the recovery algorithm. A novel maximum-likelihood decoding algorithm, the In-place algorithm, is proposed with a reduced computational complexity. A further study on the marginal number of correctable erasures by the In-place algoritinn determines a lower bound of the average number of correctable erasures. Following the spirit in search of the most likable codeword based on the received vector, we propose a new branch-evaluation- search-on-the-code-tree (BESOT) algorithm, which is powerful enough to approach the ML performance for all linear block codes. To maximise the recovery capability of the In-place algorithm in network transmissions, we propose the product packetisation structure to reconcile the computational complexity of the In-place algorithm. Combined with the proposed product packetisation structure, the computational complexity is less than the quadratic complexity bound. We then extend this to application of the Rayleigh fading channel to solve the errors and erasures. By concatenating an outer code, such as BCH codes, the product-packetised RS codes have the performance of the hard-decision In-place algorithm significantly better than that of the soft-decision iterative algorithms on optimally designed LDPC codes

Synchronization for capacity -approaching coded communication systems

The dissertation concentrates on synchronization of capacity approaching error-correction codes that are deployed in noisy channels with very low signal-to-noise ratio (SNR). The major topics are symbol timing synchronization and frame synchronization.;Capacity-approaching error-correction codes, like turbo codes and low-density parity-check (LDPC) codes, are capable of reaching very low bit error rates and frame error rates in noisy channels by iterative decoding. To fully achieve the potential decoding capability of Turbo codes and LDPC codes, proper symbol timing synchronization, frame synchronization and channel state estimation are required. The dissertation proposes a joint estimator of symbol time delay and channel SNR for symbol timing recovery, and a maximum a posteriori (MAP) frame synchronizer for frame synchronization.;Symbol timing recovery is implemented by sampling and interpolation. The received signal is sampled multiple times per symbol period with unknown delay and unknown SNR. A joint estimator estimates the time delay and the SNR. The signal is rebuilt by interpolating available samples using estimated time delay. The intermediate decoding results enable decision-feedback estimation. The estimates of time delay and SNR are refined by iterative processing. This refinement improves the system performance significantly.;Usually the sampling rate is assumed to be a strict integer multiple of the symbol rate. However, in a practical system the local oscillators in the transmitter and the receiver may have random drifts. Therefore the sampling rate is no longer an exact multiple of the symbol rate, and the sampling time follows a random walk. This random walk may harm the system performance severely. The dissertation analyzes the effect of random time walks and proposes to mitigate the effect by overlapped sliding windows and iterative processing.;Frame synchronization is required to find the correct boundaries of codewords. MAP frame synchronization in the sense of minimizing the frame sync failure rate is investigated. The MAP frame synchronizer explores low-density parity-check attributes of the capacity-approaching codes. The accuracy of frame synchronization is adequate for considered coded systems to work reliably under very low SNR

Studies in Error Correction Coding

For a proper understanding of the implementation of error correction coding schemes, a basic knowledge of communication channels and networks is necessary. Communication channels incur several types of errors, including noise and signal attenuation. Consequently, the benefits of a particular error control scheme are determined by the errors which occur most frequently. First, the types of transmissions across which errors occur will be considered. Subsequently, the types of errors that can appear during these transmissions and a short discussion of the cause of errors are necessary to understand the several types of errors that can occur. Afterward, the implementation of several major coding schemes will be discussed, including block codes, linear codes, and convolutional codes. Convolutional codes will specifically be discussed in terms of turbo codes and low-density parity check codes. Lastly, research of error correction coding schemes will involve several kinds of resources, including textbooks, journal articles, and technical publications. These resources will be used for the understanding of a practical implementation of an error correction coding scheme