A graph-based aspect interference detection approach for UML-based aspect-oriented models

Aspect Oriented Modeling (AOM) techniques facilitate separate modeling of concerns and allow for a more flexible composition of these than traditional modeling technique. While this improves the understandability of each submodel, in order to reason about the behavior of the composed system and to detect conflicts among submodels, automated tool support is required. Current techniques for conflict detection among aspects generally have at least one of the following weaknesses. They require to manually model the abstract semantics for each system; or they derive the system semantics from code assuming one specific aspect-oriented language. Defining an extra semantics model for verification bears the risk of inconsistencies between the actual and the verified design; verifying only at implementation level hinders fixng errors in earlier phases. We propose a technique for fully automatic detection of conflicts between aspects at the model level; more specifically, our approach works on UML models with an extension for modeling pointcuts and advice. As back-end we use a graph-based model checker, for which we have defined an operational semantics of UML diagrams, pointcuts and advice. In order to simulate the system, we automatically derive a graph model from the diagrams. The result is another graph, which represents all possible program executions, and which can be verified against a declarative specification of invariants.\ud To demonstrate our approach, we discuss a UML-based AOM model of the "Crisis Management System" and a possible design and evolution scenario. The complexity of the system makes con°icts among composed aspects hard to detect: already in the case of two simulated aspects, the state space contains 623 di®erent states and 9 different execution paths. Nevertheless, in case the right pruning methods are used, the state-space only grows linearly with the number of aspects; therefore, the automatic analysis scales

On-Chip Transparent Wire Pipelining (invited paper)

Wire pipelining has been proposed as a viable mean to break the discrepancy between decreasing gate delays and increasing wire delays in deep-submicron technologies. Far from being a straightforwardly applicable technique, this methodology requires a number of design modifications in order to insert it seamlessly in the current design flow. In this paper we briefly survey the methods presented by other researchers in the field and then we thoroughly analyze the solutions we recently proposed, ranging from system-level wire pipelining to physical design aspects

A case study for NoC based homogeneous MPSoC architectures

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processo

Controlling Concurrent Change - A Multiview Approach Toward Updatable Vehicle Automation Systems

The development of SAE Level 3+ vehicles [{SAE}, 2014] poses new challenges not only for the functional development, but also for design and development processes. Such systems consist of a growing number of interconnected functional, as well as hardware and software components, making safety design increasingly difficult. In order to cope with emergent behavior at the vehicle level, thorough systems engineering becomes a key requirement, which enables traceability between different design viewpoints. Ensuring traceability is a key factor towards an efficient validation and verification of such systems. Formal models can in turn assist in keeping track of how the different viewpoints relate to each other and how the interplay of components affects the overall system behavior. Based on experience from the project Controlling Concurrent Change, this paper presents an approach towards model-based integration and verification of a cause effect chain for a component-based vehicle automation system. It reasons on a cross-layer model of the resulting system, which covers necessary aspects of a design in individual architectural views, e.g. safety and timing. In the synthesis stage of integration, our approach is capable of inserting enforcement mechanisms into the design to ensure adherence to the model. We present a use case description for an environment perception system, starting with a functional architecture, which is the basis for componentization of the cause effect chain. By tying the vehicle architecture to the cross-layer integration model, we are able to map the reasoning done during verification to vehicle behavior

Realizing live sequence charts in SystemVerilog.

The design of an embedded control system starts with an investigation of properties and behaviors of the process evolving within its environment, and an analysis of the requirement for its safety performance. In early stages, system requirements are often specified as scenarios of behavior using sequence charts for different use cases. This specification must be precise, intuitive and expressive enough to capture different aspects of embedded control systems. As a rather rich and useful extension to the classical message sequence charts, live sequence charts (LSC), which provide a rich collection of constructs for specifying both possible and mandatory behaviors, are very suitable for designing an embedded control system. However, it is not a trivial task to realize a high-level design model in executable program codes effectively and correctly. This paper tackles the challenging task by providing a mapping algorithm to automatically synthesize SystemVerilog programs from given LSC specifications

Metamodel for Tracing Concerns across the Life Cycle

Several aspect-oriented approaches have been proposed to specify aspects at different phases in the software life cycle. Aspects can appear within a phase, be refined or mapped to other aspects in later phases, or even disappear.\ud Tracing aspects is necessary to support understandability and maintainability of software systems. Although several approaches have been introduced to address traceability of aspects, two important limitations can be observed. First, tracing is not yet tackled for the entire life cycle. Second, the traceability model that is applied usually refers to elements of specific aspect languages, thereby limiting the reusability of the adopted traceability model.We propose the concern traceability metamodel (CTM) that enables traceability of concerns throughout the life cycle, and which is independent from the aspect languages that are used. CTM can be enhanced to provide additional properties for tracing, and be instantiated to define\ud customized traceability models with respect to the required aspect languages. We have implemented CTM in the tool M-Trace, that uses XML-based representations of the models and XQuery queries to represent tracing information. CTM and M-Trace are illustrated for a Concurrent Versioning System to trace aspects from the requirements level to architecture design level and the implementation

Survey of Spectrum Sharing for Inter-Technology Coexistence

Increasing capacity demands in emerging wireless technologies are expected to be met by network densification and spectrum bands open to multiple technologies. These will, in turn, increase the level of interference and also result in more complex inter-technology interactions, which will need to be managed through spectrum sharing mechanisms. Consequently, novel spectrum sharing mechanisms should be designed to allow spectrum access for multiple technologies, while efficiently utilizing the spectrum resources overall. Importantly, it is not trivial to design such efficient mechanisms, not only due to technical aspects, but also due to regulatory and business model constraints. In this survey we address spectrum sharing mechanisms for wireless inter-technology coexistence by means of a technology circle that incorporates in a unified, system-level view the technical and non-technical aspects. We thus systematically explore the spectrum sharing design space consisting of parameters at different layers. Using this framework, we present a literature review on inter-technology coexistence with a focus on wireless technologies with equal spectrum access rights, i.e. (i) primary/primary, (ii) secondary/secondary, and (iii) technologies operating in a spectrum commons. Moreover, we reflect on our literature review to identify possible spectrum sharing design solutions and performance evaluation approaches useful for future coexistence cases. Finally, we discuss spectrum sharing design challenges and suggest future research directions

Wireless information and power transfer: from scientific hypothesis to engineering practice

Recently, there has been substantial research interest in the subject of Simultaneous Wireless Information andPower Transfer (SWIPT) owing to its cross-disciplinary appeal and its wide-ranging application potential, whichmotivates this overview. More explicitly, we provide a brief survey of the state-of-the-art and introduce severalpractical transceiver architectures that may facilitate its implementation. Moreover, the most important link-levelas well as system-level design aspects are elaborated on, along with a variety of potential solutions and researchideas. We envision that the dual interpretation of Radio Frequency (RF) signals creates new opportunities as wellas challenges requiring substantial research, innovation and engineering efforts

Estimation of Defect proneness Using Design complexity Measurements in Object- Oriented Software

Software engineering is continuously facing the challenges of growing complexity of software packages and increased level of data on defects and drawbacks from software production process. This makes a clarion call for inventions and methods which can enable a more reusable, reliable, easily maintainable and high quality software systems with deeper control on software generation process. Quality and productivity are indeed the two most important parameters for controlling any industrial process. Implementation of a successful control system requires some means of measurement. Software metrics play an important role in the management aspects of the software development process such as better planning, assessment of improvements, resource allocation and reduction of unpredictability. The process involving early detection of potential problems, productivity evaluation and evaluating external quality factors such as reusability, maintainability, defect proneness and complexity are of utmost importance. Here we discuss the application of CK metrics and estimation model to predict the external quality parameters for optimizing the design process and production process for desired levels of quality. Estimation of defect-proneness in object-oriented system at design level is developed using a novel methodology where models of relationship between CK metrics and defect-proneness index is achieved. A multifunctional estimation approach captures the correlation between CK metrics and defect proneness level of software modules.Comment: 5 pages, 1 figur

Pwning Level Bosses in MATLAB: Student Reactions to a Game-Inspired Computational Physics Course

We investigated student reactions to two computational physics courses incorporating several videogame-like aspects. These included use of gaming terminology such as "levels," "weapons," and "bosses"; a game-style point system linked to course grades; a self-paced schedule with no deadlines; a mastery design in which only entirely correct attempts earn credit, but students can retry until they succeed; immediate feedback via self-test code; an assignment progression from "minions" (small, focused tasks) to "level bosses" (integrative tasks); and believable, authentic assignment scenarios. Through semi-structured interviews and course evaluations, we found that a majority of students considered the courses effective and the game-like aspects beneficial. In particular, many claimed that the point system increased their motivation; the self-paced nature caused them to reflect on their self-discipline; the possibility and necessity of repeating assignments until perfect aided learning; and the authentic tasks helped them envision using course skills in their professional futures.Comment: Accepted for publication in the proceedings of the 2014 Physics Education Research Conference (PERC