Floating-Gate Design and Linearization for Reconfigurable Analog Signal Processing

Analog and mixed-signal integrated circuits have found a place in modern electronics design as a viable alternative to digital pre-processing. With metrics that boast high accuracy and low power consumption, analog pre-processing has opened the door to low-power state-monitoring systems when it is utilized in place of a power-hungry digital signal-processing stage. However, the complicated design process required by analog and mixed-signal systems has been a barrier to broader applications. The implementation of floating-gate transistors has begun to pave the way for a more reasonable approach to analog design. Floating-gate technology has widespread use in the digital domain. Analog and mixed-signal use of floating-gate transistors has only become a rising field of study in recent years. Analog floating gates allow for low-power implementation of mixed-signal systems, such as the field-programmable analog array, while simultaneously opening the door to complex signal-processing techniques. The field-programmable analog array, which leverages floating-gate technologies, is demonstrated as a reliable replacement to signal-processing tasks previously only solved by custom design. Living in an analog world demands the constant use and refinement of analog signal processing for the purpose of interfacing with digital systems. This work offers a comprehensive look at utilizing floating-gate transistors as the core element for analog signal-processing tasks. This work demonstrates the floating gate\u27s merit in large reconfigurable array-driven systems and in smaller-scale implementations, such as linearization techniques for oscillators and analog-to-digital converters. A study on analog floating-gate reliability is complemented with a temperature compensation scheme for implementing these systems in ever-changing, realistic environments

Blind multi-user combining at the base station for asynchronous CDMA systems

This paper studies the potential benefits of antenna arrays in cellular CDMA communications and proposes a powerful scheme to undertake the array processing at the base station in CDMA mobile systems. The proposed technique exploits the temporal structure of CDMA signals. The necessary information is extracted directly from the received signals, thus no training signal orPeer ReviewedPostprint (published version

Exploring Energy-Efficient Reconfigurable Architectures for DSP Algorithms

Future hand-held multimedia terminals require a very high performance on a very small energy budged. Such devices can only be realized if their entire system is energy cognisant. In this paper a reconfigurable systems-architecture for mobile multimedia systems is introduced. The Field Programmable Function Array (FPFA) is discussed in detail. Several digital signal processing algorithms are discussed and mapped on the FPFA. Also,the power radius theory about low-power design is introduced