28,938 research outputs found
A Cost- Effective Design of Reversible Programmable Logic Array
In the recent era, Reversible computing is a growing field having
applications in nanotechnology, optical information processing, quantum
networks etc. In this paper, the authors show the design of a cost effective
reversible programmable logic array using VHDL. It is simulated on xilinx ISE
8.2i and results are shown. The proposed reversible Programming logic array
called RPLA is designed by MUX gate [10] & Feynman gate for 3- inputs, which is
able to perform any reversible 3- input logic function or Boolean function.
Furthermore the quantized analysis with camparitive finding is shown for the
realized RPLA against the existing one. The result shows improvement in the
quantum cost and total logical caculation in proposed RPLA.Comment: 6 Pages, 9 Figure
AutoAccel: Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture
CPU-FPGA heterogeneous architectures are attracting ever-increasing attention
in an attempt to advance computational capabilities and energy efficiency in
today's datacenters. These architectures provide programmers with the ability
to reprogram the FPGAs for flexible acceleration of many workloads.
Nonetheless, this advantage is often overshadowed by the poor programmability
of FPGAs whose programming is conventionally a RTL design practice. Although
recent advances in high-level synthesis (HLS) significantly improve the FPGA
programmability, it still leaves programmers facing the challenge of
identifying the optimal design configuration in a tremendous design space.
This paper aims to address this challenge and pave the path from software
programs towards high-quality FPGA accelerators. Specifically, we first propose
the composable, parallel and pipeline (CPP) microarchitecture as a template of
accelerator designs. Such a well-defined template is able to support efficient
accelerator designs for a broad class of computation kernels, and more
importantly, drastically reduce the design space. Also, we introduce an
analytical model to capture the performance and resource trade-offs among
different design configurations of the CPP microarchitecture, which lays the
foundation for fast design space exploration. On top of the CPP
microarchitecture and its analytical model, we develop the AutoAccel framework
to make the entire accelerator generation automated. AutoAccel accepts a
software program as an input and performs a series of code transformations
based on the result of the analytical-model-based design space exploration to
construct the desired CPP microarchitecture. Our experiments show that the
AutoAccel-generated accelerators outperform their corresponding software
implementations by an average of 72x for a broad class of computation kernels
Genome-wide association study in two cohorts from a multi-generational mouse advanced intercross line highlights the difficulty of replication due to study-specific heterogeneity
There has been extensive discussion of the Replication Crisis in many fields, including genome-wide association studies
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