167 research outputs found
An Alternative Carry-save Arithmetic for New Generation Field Programmable Gate Arrays
In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input
LUT-based eld programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number
representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and
fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add
operation for 6-input LUT-based FPGA systems. A nite impulse response lter implementation is given to show the
performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which
is at least 2 times faster than conventional binary multiply-add implementations
Pipelined Two-Operand Modular Adders
Pipelined two-operand modular adder (TOMA) is one of basic components used in digital signal processing (DSP) systems that use the residue number system (RNS). Such modular adders are used in binary/residue and residue/binary converters, residue multipliers and scalers as well as within residue processing channels. The design of pipelined TOMAs is usually obtained by inserting an appriopriate number of latch layers inside a nonpipelined TOMA structure. Hence their area is also determined by the number of latches and the delay by the number of latch layers. In this paper we propose a new pipelined TOMA that is based on a new TOMA, that has the smaller area and smaller delay than other known structures. Comparisons are made using data from the very large scale of integration (VLSI) standard cell library
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