Concatenated Turbo/LDPC codes for deep space communications: performance and implementation

Deep space communications require error correction codes able to reach extremely low bit-error-rates, possibly with a steep waterfall region and without error floor. Several schemes have been proposed in the literature to achieve these goals. Most of them rely on the concatenation of different codes that leads to high hardware implementation complexity and poor resource sharing. This work proposes a scheme based on the concatenation of non-custom LDPC and turbo codes that achieves excellent error correction performance. Moreover, since both LDPC and turbo codes can be decoded with the BCJR algorithm, our preliminary results show that an efficient hardware architecture with high resource reuse can be designe

Multi-level Turbo Decoding Assisted Soft Combining Aided Hybrid ARQ

Hybrid Automatic Repeat reQuest (ARQ) plays an essential role in error control. Combining the incorrectly received packet replicas in hybrid ARQ has been shown to reduce the resultant error probability, while improving the achievable throughput. Hence, in this contribution, multi-level turbo codes have been amalgamated both with hybrid ARQ and efficient soft combining techniques for taking into account the Log- Likelihood Ratios (LLRs) of retransmitted packet replicas. In this paper, we present a soft combining aided hybrid ARQ scheme based on multi-level turbo codes, which avoid the capacity loss of the twin-level turbo codes that are typically employed in hybrid ARQ schemes. More specifically, the proposed receiver dynamically appends an additional parallel concatenated Bahl, Cocke, Jelinek and Raviv (BCJR) algorithm based decoder in order to fully exploit each retransmission, thereby forming a multi-level turbo decoder. Therefore, all the extrinsic information acquired during the previous BCJR operations will be used as a priori information by the additional BCJR decoders, whilst their soft output iteratively enhances the a posteriori information generated by the previous decoding stages. We also present link- level Packet Loss Ratio (PLR) and throughput results, which demonstrate that our scheme outperforms some of the previously proposed benchmarks

VLSI implementation of a multi-mode turbo/LDPC decoder architecture

Flexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, reconfigurable architectures for the physical layer are an attractive solution not only to switch among different coding modes but also to achieve interoperability. This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding. The novel contributions of this paper are: i) tackling the reconfiguration issue introducing a formal and systematic treatment that, to the best of our knowledge, was not previously addressed; ii) proposing a reconfigurable NoCbased turbo/LDPC decoder architecture and showing that wide flexibility can be achieved with a small complexity overhead. Obtained results show that dynamic switching between most of considered communication standards is possible without pausing the decoding activity. Moreover, post-layout results show that tailoring the proposed architecture to the WiMAX standard leads to an area occupation of 2.75 mm2 and a power consumption of 101.5 mW in the worst case

On chip interconnects for multiprocessor turbo decoding architectures

International audienc

Configurable and Scalable Turbo Decoder for 4G Wireless Receivers

The increasing requirements of high data rates and quality of service (QoS) in fourth-generation (4G) wireless communication require the implementation of practical capacity approaching codes. In this chapter, the application of Turbo coding schemes that have recently been adopted in the IEEE 802.16e WiMax standard and 3GPP Long Term Evolution (LTE) standard are reviewed. In order to process several 4G wireless standards with a common hardware module, a reconfigurable and scalable Turbo decoder architecture is presented. A parallel Turbo decoding scheme with scalable parallelism tailored to the target throughput is applied to support high data rates in 4G applications. High-level decoding parallelism is achieved by employing contention-free interleavers. A multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. A new on-line address generation technique is introduced to support multiple Turbo interleaving patterns, which avoids the interleaver address memory that is typically necessary in the traditional designs. Design trade-offs in terms of area and power efficiency are analyzed for different parallelism and clock frequency goals

On the Convergence Speed of Turbo Demodulation with Turbo Decoding

Iterative processing is widely adopted nowadays in modern wireless receivers for advanced channel codes like turbo and LDPC codes. Extension of this principle with an additional iterative feedback loop to the demapping function has proven to provide substantial error performance gain. However, the adoption of iterative demodulation with turbo decoding is constrained by the additional implied implementation complexity, heavily impacting latency and power consumption. In this paper, we analyze the convergence speed of these combined two iterative processes in order to determine the exact required number of iterations at each level. Extrinsic information transfer (EXIT) charts are used for a thorough analysis at different modulation orders and code rates. An original iteration scheduling is proposed reducing two demapping iterations with reasonable performance loss of less than 0.15 dB. Analyzing and normalizing the computational and memory access complexity, which directly impact latency and power consumption, demonstrates the considerable gains of the proposed scheduling and the promising contributions of the proposed analysis.Comment: Submitted to IEEE Transactions on Signal Processing on April 27, 201

Turbo Decoding and Detection for Wireless Applications

A historical perspective of turbo coding and turbo transceivers inspired by the generic turbo principles is provided, as it evolved from Shannon’s visionary predictions. More specifically, we commence by discussing the turbo principles, which have been shown to be capable of performing close to Shannon’s capacity limit. We continue by reviewing the classic maximum a posteriori probability decoder. These discussions are followed by studying the effect of a range of system parameters in a systematic fashion, in order to gauge their performance ramifications. In the second part of this treatise, we focus our attention on the family of iterative receivers designed for wireless communication systems, which were partly inspired by the invention of turbo codes. More specifically, the family of iteratively detected joint coding and modulation schemes, turbo equalization, concatenated spacetime and channel coding arrangements, as well as multi-user detection and three-stage multimedia systems are highlighted