Area-Time Optimal VLSI Networks for Matrix Multiplication and Inversion of Triangular Matrices

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryJoint Services Electronics Program / N00014-79-C-0424National Science Foundation / MCS 78-1364

Pade-Type Model Reduction of Second-Order and Higher-Order Linear Dynamical Systems

A standard approach to reduced-order modeling of higher-order linear dynamical systems is to rewrite the system as an equivalent first-order system and then employ Krylov-subspace techniques for reduced-order modeling of first-order systems. While this approach results in reduced-order models that are characterized as Pade-type or even true Pade approximants of the system's transfer function, in general, these models do not preserve the form of the original higher-order system. In this paper, we present a new approach to reduced-order modeling of higher-order systems based on projections onto suitably partitioned Krylov basis matrices that are obtained by applying Krylov-subspace techniques to an equivalent first-order system. We show that the resulting reduced-order models preserve the form of the original higher-order system. While the resulting reduced-order models are no longer optimal in the Pade sense, we show that they still satisfy a Pade-type approximation property. We also introduce the notion of Hermitian higher-order linear dynamical systems, and we establish an enhanced Pade-type approximation property in the Hermitian case

Spiking Neural Networks for Inference and Learning: A Memristor-based Design Perspective

On metrics of density and power efficiency, neuromorphic technologies have the potential to surpass mainstream computing technologies in tasks where real-time functionality, adaptability, and autonomy are essential. While algorithmic advances in neuromorphic computing are proceeding successfully, the potential of memristors to improve neuromorphic computing have not yet born fruit, primarily because they are often used as a drop-in replacement to conventional memory. However, interdisciplinary approaches anchored in machine learning theory suggest that multifactor plasticity rules matching neural and synaptic dynamics to the device capabilities can take better advantage of memristor dynamics and its stochasticity. Furthermore, such plasticity rules generally show much higher performance than that of classical Spike Time Dependent Plasticity (STDP) rules. This chapter reviews the recent development in learning with spiking neural network models and their possible implementation with memristor-based hardware

A New Low-Complexity Decodable Rate-5/4 STBC for Four Transmit Antennas with Nonvanishing Determinants

The use of Space-Time Block Codes (STBCs) increases significantly the optimal detection complexity at the receiver unless the low-complexity decodability property is taken into consideration in the STBC design. In this paper we propose a new low-complexity decodable rate-5/4 full-diversity 4 x 4 STBC. We provide an analytical proof that the proposed code has the Non-Vanishing-Determinant (NVD) property, a property that can be exploited through the use of adaptive modulation which changes the transmission rate according to the wireless channel quality. We compare the proposed code to the best existing low-complexity decodable rate-5/4 full-diversity 4 x 4 STBC in terms of performance over quasi-static Rayleigh fading channels, worst- case complexity, average complexity, and Peak-to-Average Power Ratio (PAPR). Our code is found to provide better performance, lower average decoding complexity, and lower PAPR at the expense of a slight increase in worst-case decoding complexity.Comment: 5 pages, 2 figures and 1 table; IEEE Global Telecommunications Conference (GLOBECOM 2011), 201

Recent Advances in Graph Partitioning

We survey recent trends in practical algorithms for balanced graph partitioning together with applications and future research directions

Mathematical representation for VLSI arrays

Journal ArticleThis paper introduces a methodology for mapping algorithmic description into a concurrent implementation on silicon. This methodology can help in the solution of important problems using a new technique for the representation of highly parallel networks. This new approach for the representation of computational networks was inspired by the systolic array approach [H. T. Kung & Leiserson 78], and by the linear approach to computational networks [Cohen 78]. It creates tools which will enable the creation of new high performance implementations as well as verification tools. This approach is more complex than the linear approach [Gill 66, Cohen 78]. but can also be used to verify computation networks

Parallel Searching-Based Sphere Detector for MIMO Downlink OFDM Systems

In this paper, implementation of a detector with parallel partial candidate-search algorithm is described. Two fully independent partial candidate search processes are simultaneously employed for two groups of transmit antennas based on QR decomposition (QRD) and QL decomposition (QLD) of a multiple-input multiple-output (MIMO) channel matrix. By using separate simultaneous candidate searching processes, the proposed implementation of QRD-QLD searching-based sphere detector provides a smaller latency and a lower computational complexity than the original QRD-M detector for similar error-rate performance in wireless communications systems employing four transmit and four receive antennas with 16-QAM or 64-QAM constellation size. It is shown that in coded MIMO orthogonal frequency division multiplexing (MIMO OFDM) systems, the detection latency and computational complexity of a receiver can be substantially reduced by using the proposed QRD-QLD detector implementation. The QRD-QLD-based sphere detector is also implemented using Field Programmable Gate Array (FPGA) and application specific integrated circuit (ASIC), and its hardware design complexity is compared with that of other sphere detectors reported in the literature.Nokia Renesas MobileTexas InstrumentsXilinxNational Science Foundatio

Fault Secure Encoder and Decoder for NanoMemory Applications

Memory cells have been protected from soft errors for more than a decade; due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and must also be protected. We introduce a new approach to design fault-secure encoder and decoder circuitry for memory designs. The key novel contribution of this paper is identifying and defining a new class of error-correcting codes whose redundancy makes the design of fault-secure detectors (FSD) particularly simple. We further quantify the importance of protecting encoder and decoder circuitry against transient errors, illustrating a scenario where the system failure rate (FIT) is dominated by the failure rate of the encoder and decoder. We prove that Euclidean geometry low-density parity-check (EG-LDPC) codes have the fault-secure detector capability. Using some of the smaller EG-LDPC codes, we can tolerate bit or nanowire defect rates of 10% and fault rates of 10^(-18) upsets/device/cycle, achieving a FIT rate at or below one for the entire memory system and a memory density of 10^(11) bit/cm^2 with nanowire pitch of 10 nm for memory blocks of 10 Mb or larger. Larger EG-LDPC codes can achieve even higher reliability and lower area overhead