Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders

Polar codes are a recently proposed family of provably capacity-achieving error-correction codes that received a lot of attention. While their theoretical properties render them interesting, their practicality compared to other types of codes has not been thoroughly studied. Towards this end, in this paper, we perform a comparison of polar decoders against LDPC and Turbo decoders that are used in existing communications standards. More specifically, we compare both the error-correction performance and the hardware efficiency of the corresponding hardware implementations. This comparison enables us to identify applications where polar codes are superior to existing error-correction coding solutions as well as to determine the most promising research direction in terms of the hardware implementation of polar decoders.Comment: Fixes small mistakes from the paper to appear in the proceedings of IEEE WCNC 2017. Results were presented in the "Polar Coding in Wireless Communications: Theory and Implementation" Worksho

Energy-Efficient Soft-Assisted Product Decoders

We implement a 1-Tb/s 0.63-pJ/bit soft-assisted product decoder in a 28-nm technology. The decoder uses one bit of soft information to improve its net coding gain by 0.2 dB, reaching 10.3-10.4 dB, which is similar to that of more complex hard-decision staircase decoders

A Vision for 5G Channel Coding

Channel coding is a vital but complex component of cellular communication systems, which is used for correcting the communication errors that are caused by noise, interference and poor signal strength. The turbo code was selected as the main channel code in 3G and 4G cellular systems, but the 3GPP standardization group is currently debating whether it should be replaced by the Low Density Parity Check (LDPC) code in 5G. This debate is being driven by the requirements for 5G, which include throughputs of up to 20 Gbps in the downlink to user devices, ultra-low latencies, as well as much greater flexibility to support diverse use-cases, including broadband data, Internet of Things (IoT), vehicular communications and cloud computing. In our previous white paper, we demonstrated that flexible turbo codes can achieve these requirements with superior hardware- and energy-efficiencies than flexible LDPC decoders. However, the proponents of LDPC codes have highlighted that inflexible LDPC decoders can achieve throughputs of 20 Gbps with particularly attractive hardware- and energy- efficiencies. This white paper outlines a vision for 5G, in which channel coding is provided by a flexible turbo code for most use-cases, but which is supported by an inflexible LDPC code for 20 Gbps downlink use-cases, such as fixed wireless broadband. We demonstrate that this approach can meet all of the 5G requirements, while offering hardware- and energy-efficiencies that are significantly better than those of an LDPC-only solution. Furthermore, the proposed approach benefits from synergy with the 3G and 4G turbo code, as well as a significantly faster time-to-market for 5G. These benefits translate to a 5G that is significantly more capable, significantly easier to deploy and significantly lower cost

Modeling and Energy Optimization of LDPC Decoder Circuits with Timing Violations

This paper proposes a "quasi-synchronous" design approach for signal processing circuits, in which timing violations are permitted, but without the need for a hardware compensation mechanism. The case of a low-density parity-check (LDPC) decoder is studied, and a method for accurately modeling the effect of timing violations at a high level of abstraction is presented. The error-correction performance of code ensembles is then evaluated using density evolution while taking into account the effect of timing faults. Following this, several quasi-synchronous LDPC decoder circuits based on the offset min-sum algorithm are optimized, providing a 23%-40% reduction in energy consumption or energy-delay product, while achieving the same performance and occupying the same area as conventional synchronous circuits.Comment: To appear in IEEE Transactions on Communication

Advanced Wireless Digital Baseband Signal Processing Beyond 100 Gbit/s

International audienceThe continuing trend towards higher data rates in wireless communication systems will, in addition to a higher spectral efficiency and lowest signal processing latencies, lead to throughput requirements for the digital baseband signal processing beyond 100 Gbit/s, which is at least one order of magnitude higher than the tens of Gbit/s targeted in the 5G standardization. At the same time, advances in silicon technology due to shrinking feature sizes and increased performance parameters alone won't provide the necessary gain, especially in energy efficiency for wireless transceivers, which have tightly constrained power and energy budgets. In this paper, we highlight the challenges for wireless digital baseband signal processing beyond 100 Gbit/s and the limitations of today's architectures. Our focus lies on the channel decoding and MIMO detection, which are major sources of complexity in digital baseband signal processing. We discuss techniques on algorithmic and architectural level, which aim to close this gap. For the first time we show Turbo-Code decoding techniques towards 100 Gbit/s and a complete MIMO receiver beyond 100 Gbit/s in 28 nm technology